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K6L0908C2A中文资料

Document Title

64Kx8 bit Low Power CMOS Static RAM Revision History

Revision No.

0.0

0.1

1.0

2.0

3.0

4.0

Remark

Design target

Preliminary

Final

Final History

Initial draft

Revision

Finalize

Revision

- Add 45ns part with 30pf test load.

Revision

- Change Data Sheet format :

One data sheets for industrial and commercial product

Revision

- Change Data Sheet format

- Remove 45ns part from commercial product and 100ns part

from industrial product

- Remove low power part form TSOP package

Draft Data

Novemer 28, 1993

May 13, 1994

December 1, 1994

August 12, 1995

April 15, 1996

January 9, 1998

The attached data, sheets are provided by SAMSUNG Electronics. SAMSUNG Electronics CO., LTD. reserve the right to change the specifications and products. SAMSUNG Electronics will answer to your questions about device. If you have any questions, please contact the SAMSUNG branch offices.

64Kx8 bit Low Power CMOS Static RAM

GENERAL DESCRIPTION

The K6L0908C2A families are fabricated by SAMSUNG ′s advanced CMOS process technology. The families support various operating temperature ranges and have various package types for user flexibility of system design. The families also support low data retention voltage for battery back-up operation with low data retention current.

FEATURES

? Process Technology: Poly Load ? Organization: 64Kx8

? Power Supply Voltage: 4.5~5.5V

? Low Data Retention Voltage: 2V(Min)? Three state output and TTL Compatible

? Package Type: 32-SOP-525, 32-TSOP1-0820F

PIN DESCRIPTION

Name Function CS 1, CS 2

Chip Select Inputs OE Output Enable Input WE Write Enable Input A 0~A 15Address Inputs I/O 1~I/O 8

Data Inputs/Outputs Vcc Power Vss Ground N.C

No Connection

PRODUCT FAMILY

Product Family Operating Temperature

V CC Range

Speed

Power Dissipation

PKG Type

Standby (I SB1, Max)Operating (I CC2, Max)

K6L0908C2A-L Commercial (0~70°C)

4.5 to

5.5V

55/70ns

100μA 70mA

32-SOP 32-TSOP1-F

K6L0908C2A-B 20μA K6L0908C2A-P Industrial (-40~85°C)

70ns

100μA K6L0908C2A-F

50μA

FUNCTIONAL BLOCK DIAGRAM

SAMSUNG ELECTRONICS CO., LTD. reserves the right to change products and specifications without notice.

A11A9A8A13WE CS2A15NC NC A14A12A7A6A5A4

OE A10CS1I/O8I/O7I/O6I/O5I/O4VSS I/O3I/O2I/O1A0A1A2A3

32-TSOP Type1 - Forward

32313029282726252423222120191817

12345678910111213141516

N.C A14A12A7A6A5A4A3A2A1A0I/O1I/O2I/O3VSS

VCC A15CS2WE A13A8A9A11OE A10CS1I/O8I/O7I/O6I/O5I/O4

32313029282726

252423222120191817

12345678910111213141516

32-SOP

N.C VCC

PRODUCT LIST

Commercial Temperature Products(0~70°C)Industrial Temperature Products(-40~85°C)Part Name

Function

Part Name

Function

K6L0908C2A-GL55 K6L0908C2A-GB55 K6L0908C2A-GL70 K6L0908C2A-GB70

K6L0908C2A-TB55 K6L0908C2A-TB70

32-SOP, 55ns, L-pwr 32-SOP, 55ns, LL-pwr 32-SOP, 70ns, L-pwr 32-SOP, 70ns, LL-pwr

32-TSOP1-F, 55ns, LL-pwr 32-TSOP1-F, 70ns, LL-pwr

K6L0908C2A-GP70 K6L0908C2A-GF70

K6L0908C2A -TF70

32-SOP, 70ns, L-pwr 32-SOP, 70ns, LL-pwr 32-TSOP1-F, 70ns, LL-pwr

FUNCTIONAL DESCRIPTION

1. X means don ′t care.(Must be low or high state)

CS 1CS 2OE WE I/O Pin Mode Power H X 1)X 1)X 1)High-Z Deselected Standby X 1)L X 1)X 1)High-Z Deselected Standby L H H H High-Z Output Disabled

Active L H L H Dout Read Active L

X 1)

Din

Write

Active

ABSOLUTE MAXIMUM RATINGS 1)

1. Stresses greater than those listed under "Absolute Maximum Ratings" may cause permanent damage to the device. Functional operation should be restricted to recommended operating condition. Exposure to absolute maximum rating conditions for extended periods may affect reliability.

Item

Symbol Ratings Unit Remark

Voltage on any pin relative to Vss V IN ,V OUT -0.5 to 7.0V -Voltage on Vcc supply relative to Vss V CC -0.5 to 7.0

V -Power Dissipation P D 1.0W -Storage temperature T STG -65 to 150°C -Operating Temperature T A 0 to 70°C K6L0908C2A-C -40 to 85

°C K6L0908C2A-I

Soldering temperature and time

T SOLDER

260°C, 10sec(Lead Only)

RECOMMENDED DC OPERATING CONDITIONS 1)

Note

1. Commercial Product : T A =0 to 70°C, unless otherwise specified Industrial Product : T A =-40 to 85°C, unless otherwise specified

2. Overshoot : V CC +

3.0V in case of pulse width ≤30ns 3. Undershoot : -3.0V in case of pulse width ≤30ns

4. Overshoot and undershoot are sampled, not 100% tested

Item

Symbol Min Typ Max Unit Supply voltage Vcc 4.5 5.0 5.5V Ground

Vss 000V Input high voltage V IH 2.2-Vcc+0.5V 2)

V Input low voltage

V IL

-0.53)

0.8

CAPACITANCE 1)(f=1MHz, T A =25°C)

1. Capacitance is sampled, not 100% tested

Item

Symbol Test Condition

Min Max Unit Input capacitance C IN V IN =0V -6pF Input/Output capacitance

C IO

V IO =0V

DC AND OPERATING CHARACTERISTICS

Item

Symbol Test Conditions

Min Typ Max Unit Input leakage current I LI V IN =Vss to Vcc

-1-1μA Output leakage current

I LO CS 1=V IH or CS 2=V IL or OE=V IH or WE=V IL , V IO =Vss to Vcc -1-1μA Operating power supply current I CC I IO =0mA, CS 1=V IL , CS 2=V IH , V IN =V IH or V IL

-715mA Average operating current

I CC1

Cycle time=1μs, 100% duty, I IO =0mA

CS 1≤0.2V, CS 2≥V CC -0.2V, V IN ≤0.2V or V IN ≥Vcc -0.2V

--10mA I CC2

Cycle time=Min, 100% duty, I IO =0mA, CS 1=V IL , CS 2=V IH , V IN =V IH or V IL

--70mA Output low voltage V OL I OL =2.1mA --0.4V Output high voltage V OH I OH =-1.0mA

2.4--V Standby Current(TTL)I SB CS 1=V IH , CS 2=V IL , Other inputs =V IH or V IL

--3mA Standby Current (CMOS)

K6L0908C2A-L/-B

I SB1

CS 1≥Vcc-0.2V, CS 2≥Vcc-0.2V or CS 2≤0.2V Other inputs =0 ~ Vcc Low Power

Low Low Power --2110020μA K6L0908C2A-P/-F

Low Power

Low Low Power

10050

μA

AC CHARACTERISTICS (Vcc=4.5~5.5V, K6L0908C2A-C Family:T A =0 to 70°C, K6L0908C2A-I Family:T A =-40 to 85°C)

Parameter List

Symbol

Speed Bins

Units

55ns

70ns

Min

Max Min Max Read

Read cycle time t RC 55-70-ns Address access time t AA -55-70ns Chip select to output t CO1, t CO2

-55-70ns Output enable to valid output

t OE -25-35ns Chip select to low-Z output t LZ 10-10-ns Output enable to low-Z output t OLZ 5-5-ns Chip disable to high-Z output t HZ 020025ns Output disable to high-Z output t OHZ 020025ns Output hold from address change t OH 10-10-ns Write

Write cycle time

t WC 55-70-ns Chip select to end of write t CW 45-60-ns Address set-up time t AS 0-0-ns Address valid to end of write

t AW 45-60-ns Write pulse width t WP 40-50-ns Write recovery time t WR 0-0-ns Write to output high-Z t WHZ 020025ns Data to write time overlap t DW 25-30-ns Data hold from write time t DH 0-0-ns End write to output low-Z

t OW

5-5-ns C L 1)

1. Including scope and jig capacitance

AC OPERATING CONDITIONS

TEST CONDITIONS ( Test Load and Input/Output Reference)

Input pulse level : 0.8 to 2.4V Input rising and falling time : 5ns

Input and output reference voltage :1.5V Output load(see right) : C L =100pF+1TTL

DATA RETENTION CHARACTERISTICS

1. CS 1≥Vcc-0.2V, CS 2≥Vcc-0.2V( CS 1 controlled) or CS 2≤0.2V(CS 2 controlled).

Item

Symbol

Test Condition

Min Typ Max Unit Vcc for data retention

V DR

CS 11)≥Vcc-0.2V

2.0- 5.5V

Data retention current

I DR

K6L0908C2A-L/-B

Vcc=3.0V CS 1≥Vcc-0.2V CS 2≥Vcc-0.2V or CS 2≤0.2V

L-Ver LL-Ver --10.55010μA

K6L0908C2A-P/-F

L-Ver LL-Ver

----5025Data retention set-up time t SDR See data retention waveform 0--ms

Recovery time

t RDR

Address

Data Out

TIMMING DIAGRAMS

TIMING WAVEFORM OF READ CYCLE(1) (Address Controlled , CS1=OE=V IL , WE=V IH )

TIMING WAVEFORM OF READ CYCLE(2) (WE=V IH )

Data Valid

High-Z

CS 1

Address

Data ou t

NOTES (READ CYCLE)

1. t HZ and t OHZ are defined as the time at which the outputs achieve the open circuit conditions and are not referenced to output voltage levels.

2. At any given temperature and voltage condition, t HZ (Max.) is less than t LZ (Min.) both for a given device and from device to device interconnection.

CS 2

t OH

t AA t OLZ

t LZ

t OHZ

t HZ(1,2)

t RC

t CO2

t OE

t CO1

Address

CS 1

TIMING WAVEFORM OF WRITE CYCLE(2) (CS 1 Controlled)

Address

CS 1

CS 2

Data in

Data out

Data in

Data out High-Z

High-Z

CS 2

DATA RETENTION WAVE FORM

CS 1 controlled

V CC 4.5V

2.2V V DR

CS 1GND

Address

CS 1

NOTES (WRITE CYCLE)

1. A write occurs during the overlap of a low CS 1, a high CS 2 and a low WE. A write begins at the latest transition among CS 1 goes low,CS 2 going high and WE going low : A write end at the earliest transition among CS 1 going high, CS 2 going low and WE going high,t WP is measured from the begining of write to the end of write.

2. t CW is measured from the CS 1 going low or CS 2 going high to the end of write.

3. t AS is measured from the address valid to the beginning of write.

4. t WR is measured from the end of write to the address change. t WR(1) applied in case a write ends as CS 1 or WE going high t WR(2)

applied in case a write ends as CS 2 going to low.

CS 2

Data in

Data out

High-Z High-Z

CS 2 controlled

V CC 4.5V 0.4V V DR CS 2

GND

PACKAGE DIMENSIONS

Units: millimeter(Inch) 32 PIN SMALL OUTLINE PACKAGE (525mil)

32-THIN SMALL OUTLINE PACKAGE TYPE I (0820F)