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AT29C020-90JU中文资料

Features Array?Fast Read Access Time – 70 ns

?5-volt Only Reprogramming

?Sector Program Operation

–Single Cycle Reprogram (Erase and Program)

–1024 Sectors (256 Bytes/Sector)

–Internal Address and Data Latches for 256 Bytes

?Internal Program Control and Timer

?Hardware and Software Data Protection

?Two 8K Bytes Boot Blocks with Lockout

?Fast Sector Program Cycle Time – 10 ms

?DATA Polling for End of Program Detection

?Low Power Dissipation

–40 mA Active Current

–300 μA CMOS Standby Current

?Typical Endurance > 10,000 Cycles

?Single 5V ±10% Supply

?CMOS and TTL Compatible Inputs and Outputs

?Green (Pb/Halide-free) Packaging Option

1.Description

The AT29C020 is a 5-volt-only in-system Flash programmable and erasable read-only memory (PEROM). Its 2 megabits of memory is organized as 262,144 bytes. Manu-factured with Atmel’s advanced nonvolatile CMOS technology, the device offers access times to 70 ns with power dissipation of just 220 mW over the industrial tem-perature range. When the device is deselected, the CMOS standby current is less than 300μA. Device endurance is such that any sector can typically be written to in excess of 10,000 times.

To allow for simple in-system reprogrammability, the AT29C020 does not require high input voltages for programming. Five-volt-only commands determine the operation of the device. Reading data out of the device is similar to reading from an EPROM. Reprogramming the AT29C020 is performed on a sector basis; 256 bytes of data are loaded into the device and then simultaneously programmed.

During a reprogram cycle, the address locations and 256 bytes of data are internally latched, freeing the address and data bus for other operations. Following the initiation of a program cycle, the device will automatically erase the sector and then program the latched data using an internal control timer. The end of a program cycle can be

detected, a new access for a read or program can begin.

2.Pin Configurations

Pin Name Function

A0 - A17Addresses

CE Chip Enable

OE Output Enable

WE Write Enable

I/O0 - I/O7Data Inputs/Outputs

NC No Connect

2.132-lead PLCC Top View

2.232-lead TSOP (Type 1) Top View

2AT29C020

AT29C020 3.Block Diagram

4.Device Operation

4.1Read

The AT29C020 is accessed like an EPROM. When CE and OE are low and WE is high, the data

stored at the memory location determined by the address pins is asserted on the outputs. The

outputs are put in the high impedance state whenever CE or OE is high. This dual-line control

gives designers flexibility in preventing bus contention.

4.2Byte Load

Byte loads are used to enter the 256 bytes of a sector to be programmed or the software codes

CE or WE low (respectively) and OE high. The address is latched on the falling edge of CE or

4.3Program

The device is reprogrammed on a sector basis. If a byte of data within a sector is to be changed,

data for the entire sector must be loaded into the device. Any byte that is not loaded during the

programming of its sector will be indeterminate. Once the bytes of a sector are loaded into the

device, they are simultaneously programmed during the internal programming period. After the

first data byte has been loaded into the device, successive bytes are entered in the same man-

150 μs of the low-to-high transition of WE (or CE) of the preceding byte. If a high-to-low transi-

tion is not detected within 150 μs of the last low-to-high transition, the load period will end and

the internal programming period will start. A8 to A17 specify the sector address. The sector

address must be valid during each high-to-low transition of WE (or CE). A0 to A7 specify the

byte address within the sector. The bytes may be loaded in any order; sequential loading is not

required. Once a programming operation has been initiated, and for the duration of t WC, a read

operation will effectively be a polling operation.

4.4Software Data Protection

A software controlled data protection feature is available on the AT29C020. Once the software

protection is enabled a software algorithm must be issued to the device before a program may

be performed. The software protection feature may be enabled or disabled by the user; when

shipped from Atmel, the software data protection feature is disabled. To enable the software

data protection, a series of three program commands to specific addresses with specific data

must be performed. After the software data protection is enabled the same three program com-

mands must begin each program cycle in order for the programs to occur. All software program

commands must obey the sector program timing specifications. Once set, the software data pro-

tection feature remains active unless its disable command is issued. Power transitions will not

reset the software data protection feature; however, the software feature will guard against inad-

vertent program cycles during power transitions.

After setting SDP, any attempt to write to the device without the 3-byte command sequence will

start the internal write timers. No data will be written to the device; however, for the duration of

t WC, a read operation will effectively be a polling operation.

After the software data protection’s 3-byte command code is given, a sector of data is loaded

into the device using the sector program timing specifications.

4.5Hardware Data Protection

Hardware features protect against inadvertent programs to the AT29C020 in the following ways:

(a) V CC sense – if V CC is below 3.8V (typical), the program function is inhibited; (b) V CC power on

delay – once V CC has reached the V CC sense level, the device will automatically time out 5 ms

high inhibits program cycles; and (d) Noise filter – pulses of less than 15 ns (typical) on the WE

4.6Product Identification

The product identification mode identifies the device and manufacturer as Atmel. It may be

accessed by hardware or software operation. The hardware operation mode can be used by an

external programmer to identify the correct programming algorithm for the Atmel product.

In addition, users may wish to use the software product identification mode to identify the part

(i.e. using the device code), and have the system software use the appropriate sector size for

program operations. In this manner, the user can have a common board design for 256K to

4-megabit densities and, with each density’s sector size in a memory map, have the system soft-

ware apply the appropriate sector size.

For details, see Operating Modes (for hardware operation) or Software Product Identification.

The manufacturer and device code is the same for both modes.

4.7DATA Polling

The AT29C020 features DATA polling to indicate the end of a program cycle. During a program

cycle an attempted read of the last byte loaded will result in the complement of the loaded data

on I/O7. Once the program cycle has been completed, true data is valid on all outputs and the

4.8Toggle Bit

In addition to DATA polling the AT29C020 provides another method for determining the end of a

program or erase cycle. During a program or erase operation, successive attempts to read data

from the device will result in I/O6 toggling between one and zero. Once the program cycle has

completed, I/O6 will stop toggling and valid data will be read. Examining the toggle bit may begin

at any time during a program cycle.

4AT29C020

AT29C020

4.9

Optional Chip Erase Mode

The entire device can be erased by using a 6-byte software code. Please see Software Chip Erase application note for details.

4.10Boot Block Programming Lockout

The AT29C020 has two designated memory blocks that have a programming lockout feature. This feature prevents programming of data in the designated block once the feature has been enabled. Each of these blocks consists of 8K bytes; the programming lockout feature can be set independently for either block. While the lockout feature does not have to be activated, it can be activated for either or both blocks.

These two 8K memory sections are referred to as boot blocks . Secure code which will bring up a system can be contained in a boot block. The AT29C020 blocks are located in the first 8K bytes of memory and the last 8K bytes of memory. The boot block programming lockout feature can therefore support systems that boot from the lower addresses of memory or the higher addresses. Once the programming lockout feature has been activated, the data in that block can no longer be erased or programmed; data in other memory locations can still be changed through the regular programming methods. To activate the lockout feature, a series of seven program commands to specific addresses with specific data must be performed. Please see Boot Block Lockout Feature Enable Algorithm.

If the boot block lockout feature has been activated on either block, the chip erase function will be disabled.

4.10.1

Boot Block Lockout Detection

A software method is available to determine whether programming of either boot block section is locked out. See Software Product Identification Entry and Exit sections. When the device is in the software product identification mode, a read from location 00002H will show if programming the lower address boot block is locked out while reading location 3FFF2H will do so for the upper boot block. If the data is FE, the corresponding block can be programmed; if the data is FF, the program lockout feature has been activated and the corresponding block cannot be pro-grammed. The software product identification exit mode should be used to return to standard operation.

5.Absolute Maximum Ratings*

T emperature Under Bias...............................-55°C to +125°C *NOTICE:

Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent dam-age to the device. This is a stress rating only and functional operation of the device at these or any other conditions beyond those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability.

Storage T emperature....................................-65°C to +150°C All Input Voltages (including NC Pins)

with Respect to Ground...................................-0.6V to +6.25V All Output Voltages

with Respect to Ground.............................-0.6V to V CC + 0.6V Voltage on OE

with Respect to Ground...................................-0.6V to +13.5V

AT29C020

Notes:

1.X can be V IL or V IH .

2.Refer to AC Programming Waveforms.

3.V H = 12.0V ± 0.5V .

4.Manufacturer Code: 1F , Device Code: DA.

5.See details under Software Product Identification Entry/Exit.

6.DC and AC Operating Range

AT29C020-70

AT29C020-90Operating T emperature (Case)Industrial

-40°C - 85°C -40°C - 85°C V CC Power Supply

5V ± 10%

7.Operating Modes

Mode CE OE WE Ai I/O Read V IL V IL V IH Ai D OUT Program (2)V IL V IH V IL Ai D IN 5V Chip Erase V IL V IH V IL Ai Standby/Write Inhibit V IH X (1)X X

High Z

Program Inhibit X X V IH Program Inhibit X V IL X Output Disable X

V IH

High Z

Product Identification Hardware

V IL V IL V IH

A1 - A17 = V IL , A9 = V H ,(3) A0 = V IL Manufacturer Code (4)

A1 - A17 = V IL , A9 = V H , A0 = V IH

Device Code (4) Software (5)

A0 = V IL Manufacturer Code (4)

A0 = V IH

Device Code (4)

8.DC Characteristics

Symbol Parameter Condition Min

Max Units I LI Input Load Current V IN = 0V to V CC 10μA I LO Output Leakage Current V I/O = 0V to V CC

10μA I SB1V CC Standby Current CMOS CE = V CC - 0.3V to V CC 300μA I SB2V CC Standby Current TTL CE = 2.0V to V CC 3mA I CC V CC Active Current f = 5 MHz; I OUT = 0 mA

40mA V IL Input Low Voltage 0.8

V V IH Input High Voltage 2.0

V V OL Output Low Voltage I OL = 2.1 mA 0.45

V V OH1Output High Voltage I OH = -400 μA

2.4V V OH2

Output High Voltage CMOS

I OH = -100 μA; V CC = 4.5V

4.2V

AT29C020

10.AC Read Waveforms (1)(2)(3)(4)

Notes:

1.ACC - t CE after the address transition without impact on t ACC .

2.CE - t OE CE or by t ACC - t OE after an address change

without impact on t ACC .3.t DF is specified from OE or CE whichever occurs first (CL = 5 pF).4.This parameter is characterized and is not 100% tested.

9.AC Read Characteristics

Symbol Parameter

AT29C020-70

AT29C020-90Units Min Max Min

Max t ACC Address to Output Delay 0

7090ns t CE (1)CE to Output Delay 7090ns t OE (2)OE to Output Delay 040050ns t DF (3)(4)CE or OE to Output Float

025

030

ns t OH

Output Hold from OE, CE or Address, whichever occurred first

11.Input Test Waveforms and Measurement Level

R F

12.Output Test Load

13.Pin Capacitance

f = 1 MHz, T = 25°C(1)

Symbol Typ Max Units Conditions C IN46pF V IN = 0V C OUT812pF V OUT = 0V Note: 1.This parameter is characterized and is not 100% tested.

8AT29C020

AT29C020

15.AC Byte Load Waveforms

15.1

WE Controlled

15.214.AC Byte Load Characteristics

Symbol Parameter

Min Max

Units t AS , t OES Address, OE Set-up Time 0ns t AH Address Hold Time 50ns t CS Chip Select Set-up Time 0ns t CH Chip Select Hold Time 0ns t WP Write Pulse Width (WE or CE)90ns t DS Data Set-up Time 50ns t DH , t OEH Data, OE Hold Time 0ns t WPH

Write Pulse Width High

100

AT29C020

17.Program Cycle Waveforms (1)(2)(3)

Notes: 1.2.3.All words that are not loaded within the sector being programmed will be indeterminate.

16.Program Cycle Characteristics

Symbol Parameter Min

Max Units t WC Write Cycle Time 10

ms t AS Address Set-up Time 0ns t AH Address Hold Time 50ns t DS Data Set-up Time 50ns t DH Data Hold Time 0ns t WP Write Pulse Width 90

ns t BLC Byte Load Cycle Time 150

μs t WPH

Write Pulse Width High

100

AT29C020

18.Software Data Protection

Enable Algorithm (1)

19.Software Data Protection

Disable Algorithm (1)

20.Software Protected Program Cycle Waveform (1)(2)(3)

Notes:

1.been entered.

2.OE must be high when WE and CE are both low.

All bytes that are not loaded within the sector being programmed will be indeterminate.

Notes: 1.Data Format: I/O7 - I/O0 (Hex); Address Format: A14 - A0 (Hex).2.Data Protect state will be activated at end of program cycle.3.Data Protect state will be deactivated at end of program period.4.256 bytes of data MUST BE loaded.

AT29C020

Notes:

1.These parameters are characterized and not 100% tested.

2.See t OE spec in AC Read Characteristics.

22.

Notes:

1.These parameters are characterized and not 100% tested.

2.See t OE spec in AC Read Characteristics.

24.Toggle Bit Waveforms (1)(2)(3)

Notes: 1.2.Beginning and ending state of I/O6 may vary.

3.Any address location may be used but the address should not vary.

21.(1)

Symbol Parameter Min Typ

Max

Units t DH Data Hold Time 10ns t OEH OE Hold Time 10

ns t OE OE to Output Delay (2)ns t WR Write Recovery Time

23.Toggle Bit Characteristics (1)

Symbol Parameter Min Typ

Max

Units t DH Data Hold Time 10ns t OEH OE Hold Time 10

ns t OE OE to Output Delay (2)ns t OEHP OE High Pulse 150ns t WR Write Recovery Time

0ns

AT29C020

25.Software Product Identification

Entry (1)

26.Software Product Identification

Exit (1)

Notes:

1.Data Format: I/O15 - I/O0 (Hex);

Address Format: A14 - A0 (Hex).2.A1 - A17 = V IL .

Manufacturer Code is read for A0 = V IL ; Device Code is read for A0 = V IH .

3.The device does not remain in identification mode if

powered down.4.The device returns to standard operation mode.5.Manufacturer Code is 1F . The Device Code is DA.

27.Boot Block Lockout

Feature Enable Algorithm (1)

Notes:

1.Data Format: I/O7 - I/O0 (Hex);

Address Format: A14 - A0 (Hex).

2.Lockout feature set on lower address boot block.

3.Lockout feature set on higher address boot block.

AT29C020

28.Ordering Information

28.1

Green Package Option (Pb/Halide-free)

t ACC (ns)I CC (mA)Ordering Code Package Operation Range Active Standby 70400.3A T29C020-70JU A T29C020-70TU 32J 32T Industrial (-40° to 85°C)

0.3

A T29C020-90JU A T29C020-90TU

32J 32T

Package Type

32J 32-lead, Plastic J-leaded Chip Carrier (PLCC)32T

32-lead, Thin Small Outline Package (TSOP)

AT29C020 29.Packaging Information

29.132J – PLCC

29.232T – TSOP

16AT29C020

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