宏基的板号_LA-4493

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Compal Confidential
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KALH0 /KAL90+ /KALG0 M/B Schematics Document
Intel Penryn Processor with Cantiga + DDRIII + ICH9M
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2009-3-4 REV:1.0
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Security Classification Issued Date 2008/11/24
Compal Secret Data
Deciphered Date 2009/12/31
Title
Compal Electronics, Inc. SCHEMATIC LA-4493 401689
Sheet
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THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL Size Document Number AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS Custom MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Rev D 1 of 54
Date:
Thursday, March 19, 2009
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Compal Confidential
Model Name : KALH0/KALG0/KAL90+
Fan Control
page 40
Intel Penryn Processor
uPGA-478 Package (Socket P) page
H_A#(3..35) 4,5,6
Thermal Sensor EMC 1402
page 4
Clock Generator ICS9LPRS387
page 16
1
HDMI Conn.
page 24,30
LCD Conn.
page 22
CRT Conn.
page 23
FSB 667/800/1066MHz
1
H_D#(0..63)
LVDS TMDS Card Reader JMB385
page 31 page 17,18,19,20,21
Intel Cantiga
uFCBGA-1329
Memory BUS(DDRIII) 204pin DDRIII-SO-DIMM X2
Dual Channel
BANK 0, 1, 2, 3
page 13,14 1.5V DDRIII 800/1066
LVDS PCI-Express 16X
page 7,8,9,10,11,12,13
VGA
DMI PCI-Express
C-Link
USB conn x3
USB port 0, 2, 5
page 34
Bluetooth Conn
page 35
CMOS Camera
page 22
LS-4494P
Finger Print
AES1610
2
2
Intel ICH9-M
BGA-676
page 25,26,27,28
3.3V 48MHz
USB HD Audio
3.3V 24.576MHz/48Mhz S-ATA
LAN(GbE)
ATHEROS AR8121
page 32
MINI Card x2
WLAN, Robson2
page 34
New Card Socket
page 35
GMCH HDA
port 1 port 0
page 08
port 2
MDC 1.5 Conn page 38
HDA Codec
ALC888S-VC
page 39
VGA HDA
page 18
RJ45
page 33
ESATA Conn. page 35
CDROM Conn. page 29
SATA HDD Conn. page 29 LPC BUS
Audio AMP
page 40
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3
ENE KB926
page 36
Phone Jack x3
page 40
RTC CKT.
page 38
KAL90+
LS-4493P
KALG0
Touch Pad
KALH0
LS-4495P
Int.KBD
page 37
Power On/Off CKT.
page 38
Media/B Conn.
LS-4498P
page 37
LS-4495P
USB/B Conn.
USB port 1 LS-4921P
DC/DC Interface CKT.
page 44
FUN Conn.
LS-4492P
USB/B Conn.
USB port 1 LS-5042P
EC I/O Buffer
page 37
BIOS
page 37
FUN Conn.
LS-4494P
E_KEY/B Conn.
LS-4495P
Power Circuit DC/DC
4
LED/B Conn.
LS-5041P
CIR
page 38
FINGERPRINT/Comm
4
page 44,45,46,47,48 ,49,50,51
USB/B Conn.
USB port 1
Media/B Conn.
Compal Secret Data
2008/11/24 Deciphered Date 2009/12/31
Title
POWER SW
Page 43
Security Classification Issued Date
Compal Electronics, Inc. SCHEMATIC LA-4493
Document Number Rev D Sheet
E
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL Size AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D B DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
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STATE
SIGNAL
SLP_S1# SLP_S3# SLP_S4# SLP_S5# HIGH LOW LOW LOW LOW HIGH HIGH LOW LOW LOW HIGH HIGH HIGH LOW LOW HIGH HIGH HIGH HIGH LOW
+VALW ON ON ON ON ON
+V ON ON ON OFF OFF
+VS ON ON OFF OFF OFF
Clock ON LOW OFF OFF OFF
1
Voltage Rails
Power Plane VIN B+
1
Full ON
Description Adapter power supply (19V) AC or battery power rail for power circuit. Core voltage for CPU 0.75V switched power rail for DDR terminator 1.05V switched power rail 1.25V switched power rail 1.5V power rail for HDA/DDR3 1.5V switched power rail 1.8V GM LVDS MODULE 1.8V switched power rail 1.1V switched power rail 3.3V always on power rail 3.3V power rail for SB 3.3V power rail for LAN 3.3V switched power rail 5V always on power rail 5V switched power rail VSB always on power rail RTC power Core voltage for GPU S1 N/A N/A ON ON ON ON ON ON ON ON ON ON ON ON ON ON ON ON ON ON S3 N/A N/A OFF OFF OFF OFF ON OFF ON OFF OFF ON ON ON OFF ON OFF ON ON OFF S5 N/A N/A OFF OFF OFF OFF OFF OFF OFF OFF OFF ON* X X OFF ON* OFF ON* ON OFF
S1(Power On Suspend) S3 (Suspend to RAM) S4 (Suspend to Disk) S5 (Soft OFF)
+CPU_CORE +0.75VS +1.05VS +1.25VS +1.5V +1.5VS +1.8V +1.8VS +1.1VS +3VALW +3V +3V_LAN +3VS +5VALW +5VS +VSB
Board ID / SKU ID Table for AD channel
Vcc Ra/Rc/Re
Board ID
0 1 2 3 4 5 6 7
3.3V +/- 5% 100K +/- 5% Rb / Rd / Rf 0 8.2K +/- 5% 18K +/- 5% 33K +/- 5% 56K +/- 5% 100K +/- 5% 200K +/- 5% NC
V AD_BID min 0 V 0.216 V 0.436 V 0.712 V 1.036 V 1.453 V 1.935 V 2.500 V
V AD_BID typ 0 V 0.250 V 0.503 V 0.819 V 1.185 V 1.650 V 2.200 V 3.300 V
V AD_BID max 0 V 0.289 V 0.538 V 0.875 V 1.264 V 1.759 V 2.341 V 3.300 V
2
2
+RTCVCC +VGA_CORE
BOARD ID Table
Note : ON* means that this power plane is ON only with AC power available, otherwise it is OFF.
BTO Option Table
PCB Revision 0.1 0.2 0.3 1.0 1A BTO Item KAL90 UMA PM@ ALC888VC ALC888VB AR8121 AR8112 ALC268 GL40 GM45 KAL90-G0 KAL90-H0 KALG0 KALH0 ALC268 BOM Structure KAL90@ GM@ PM@ 888VC@ 888VB@ 8121@ 8112@ 268@ GL40@ GM45@ KAL90_G0@ KAL90_H0@ KALG0@ KALH0@ 268@ KAL90_90+@ KAL90_H0_G0@ KAL90+_G0 KALH0_G0 KAL90_G0_90+@ KAL90_H0_90+@ KAL90+_PCB@ KALG0_PCB@
External PCI Devices
Device IDSEL# REQ#/GNT# Interrupts
EC SM Bus1 address
Device
Smart Battery MEDIA CONSOLE
3
EC SM Bus2 address
Device
ADI ADT7421 NB9M THERMAL SENSOR
Board ID 0 1 2 3 4 5 6 7
Address
0001 011X b 1010 000X b
Address
1001 100X b
ICH9M SM Bus address
Device
Clock Generator (ICS9LPRS387, SLG8SP556V) DDR DIMM0 DDR DIMM2
3
Address
1101 001Xb 1001 000Xb 1001 010Xb
BOM Configuration Table
Project KAL90-UMA KAL90-Dis KALH0-GM45 KALH0-GL40 KALH0-PM45 KAL90+ -UMA KAL90+ -Dis KALG0 -UMA(GL40) KALG0 -Dis BOM Configuration XXXXXXXXXX:KAL90@/GM@/888VC@/8121@/GM45@ XXXXXXXXXX:KAL90@/PM@/888VC@/8121@ XXXXXXXXXX:KALH0@/GM@/888VC@/8121@/GM45@ XXXXXXXXXX:KALH0@/GM@/888VC@/8121@/GL40@ XXXXXXXXXX:KALH0@/PM@/888VC@/8121@ GM@/888VC@/8121@/GM45@/KAL90+_G0@/KAL90_90+@/KAL90_G0_90+@/KAL90_H0_90+@/KAL90+_PCB@ PM@/888VC@/8121@/KAL90+_G0@/KAL90_90+@/KAL90_G0_90+@/KAL90_H0_90+@/KAL90+_PCB@/PM45@
KALG0@/GM@/888VC@/8121@/GL40@/KAL90+_G0@/KALH0_G0@/KAL90_G0_90+@/KAL90+daz_PCB1.0@/KALG0++ KALG0@/PM@/888VC@/8121@/KAL90+_G0@/KALH0_G0@/KAL90_G0_90+@/KAL90+daz_PCB1.0@/PM45@/KALG0++
4
4
KALG0 -UMA(GM45) KALG0 -DIS(GM45)
KALG0@/GM@/888VC@/8121@/GM45@/KAL90+_G0@/KALH0_G0@/KAL90_G0_90+@/KAL90+daz_PCB1.0@/KALG0++ KALG0@/PM@/888VC@/8121@/KAL90+_G0@/KALH0_G0@/KAL90_G0_90+@/KAL90+daz_PCB1.0@/GM45@/KALG0++
Security Classification Issued Date 2008/11/24
Compal Secret Data
Deciphered Date 2009/12/31
Title
Compal Electronics, Inc. SCHEMATIC LA-4493
Document Number Rev D Sheet
E
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL Size AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D B DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
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<7>
H_A#[3..35]
H_A#[3..35] H_REQ#[0..4] H_RS#[0..2] JCPU1A H_A#3 H_A#4 H_A#5 H_A#6 H_A#7 H_A#8 H_A#9 H_A#10 H_A#11 H_A#12 H_A#13 H_A#14 H_A#15 H_A#16
<7> H_REQ#[0..4] <7> H_RS#[0..2]
D
CONTROL
<7>
H_ADSTB#0 H_REQ#0 H_REQ#1 H_REQ#2 H_REQ#3 H_REQ#4 H_A#17 H_A#18 H_A#19 H_A#20 H_A#21 H_A#22 H_A#23 H_A#24 H_A#25 H_A#26 H_A#27 H_A#28 H_A#29 H_A#30 H_A#31 H_A#32 H_A#33 H_A#34 H_A#35
J4 L5 L4 K5 M3 N2 J1 N3 P5 P2 L2 P4 P1 R1 M1 K3 H2 K2 J3 L1 Y2 U5 R3 W6 U4 Y5 U1 R4 T5 T3 W2 W5 Y4 U2 V4 W3 AA4 AB2 AA3 V1 A6 A5 C4 D5 C6 B4 A3 M4 N5 T2 V3 B2 D2 D22 D3 F6
A[3]# A[4]# A[5]# A[6]# A[7]# A[8]# A[9]# A[10]# A[11]# A[12]# A[13]# A[14]# A[15]# A[16]# ADSTB[0]# REQ[0]# REQ[1]# REQ[2]# REQ[3]# REQ[4]# A[17]# A[18]# A[19]# A[20]# A[21]# A[22]# A[23]# A[24]# A[25]# A[26]# A[27]# A[28]# A[29]# A[30]# A[31]# A[32]# A[33]# A[34]# A[35]# ADSTB[1]#
ADS# BNR# BPRI# DEFER# DRDY# DBSY# BR0# IERR# INIT# LOCK#
H1 E2 G5 H5 F21 E1 F1 D20 B3 H4 C1 F3 F4 G3 G2 G6 E4 AD4 AD3 AD1 AC4 AC2 AC1 AC5 AA6 AB3 AB5 AB6 C20
H_RESET# H_RS#0 H_RS#1 H_RS#2 H_IERR#
H_ADS# H_BNR# H_BPRI#
<7> <7> <7>
XDP/ITP SIGNALS
ADDR GROUP_0
D
H_DEFER# <7> H_DRDY# <7> H_DBSY# <7> H_BR0# H_INIT# <7> <26>
H_LOCK# <7> H_RESET# <7>
RESET# RS[0]# RS[1]# RS[2]# TRDY# HIT# HITM# BPM[0]# BPM[1]# BPM[2]# BPM[3]# PRDY# PREQ# TCK TDI TDO TMS TRST# DBR#
H_TRDY# <7> H_HIT# H_HITM# <7> <7>
ADDR GROUP_1
C
XDP_BPM#5 XDP_TCK XDP_TDI XDP_TMS XDP_TRST# XDP_DBRESET#
C
XDP_DBRESET# <27> +1.05VS
THERMAL
PROCHOT# THERMDA THERMDC THERMTRIP# D21 A24 B25 C7
H_PROCHOT# H_THERMDA H_THERMDC H_THERMTRIP# <8,26> XDP_TMS R3 R5
<7> <26> <26> <26>
H_ADSTB#1 H_A20M# H_FERR# H_IGNNE#
XDP_TDI
R2
1
2
54.9_0402_1%
A20M# FERR# IGNNE#
ICH
left NC if no ITP
1 1
@
2 2
54.9_0402_1% 54.9_0402_1%
39Ohm
<26> H_STPCLK# <26> H_INTR <26> H_NMI <26> H_SMI#
STPCLK# LINT0 LINT1 SMI# RSVD[01] RSVD[02] RSVD[03] RSVD[04] RSVD[05] RSVD[06] RSVD[07] RSVD[08] RSVD[09]
H CLK
BCLK[0] BCLK[1] A22 A21
CLK_CPU_BCLK <16> CLK_CPU_BCLK# <16>
XDP_BPM#5
H_PROCHOT# H_IERR#
R13 R18
2 2
1 1
56_0402_5% 56_0402_5%
RESERVED
Layout Note: H_THERMDA&H_THERMDC Trace / Space = 10 / 10 mil
XDP_TRST# XDP_TCK R7 R8
B
2 1
1 2
54.9_0402_1% 54.9_0402_1%
B
Penryn CONN@ +3VS C2 0.1U_0402_16V4Z 1 2
BSEL2
0 0 0
BSEL1
0 1 1
BSEL0
0 0 1
BCLK
266 200 166
H_PROCHOT#
+1.05VS H_THERMDA
U1
1
1
R17 @ 56_0402_5% C3
1 2 3 4
VDD DP DN THERM#
SMCLK SMDATA ALERT# GND
8 7 6 5 1
EC_SMB_CK2 <18,36,37> EC_SMB_DA2 <18,36,37>
2200P_0402_50V7K 2 H_THERMDC
2 R1133 10K_0402_5%
+3VS
2
2
B E
A
3
1
OCP#
<27>
EMC1402-1-ACZL-TR_MSOP8
A
Q1 MMBT3904_SOT23-3 @
C
Security Classification Issued Date 2008/11/24
Compal Secret Data
Deciphered Date 2009/12/31
Title
Compal Electronics, Inc. SCHEMATIC LA-4493
Document Number Rev D Sheet
1
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL Size AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D B DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
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H_D#[0..63] JCPU1B
D
H_D#[0..63]
<7> +CPU_CORE
JCPU1C
H_D#0 H_D#1 H_D#2 H_D#3 H_D#4 H_D#5 H_D#6 H_D#7 H_D#8 H_D#9 H_D#10 H_D#11 H_D#12 H_D#13 H_D#14 H_D#15 <7> <7> <7> H_DSTBN#0 H_DSTBP#0 H_DINV#0 H_D#16 H_D#17 H_D#18 H_D#19 H_D#20 H_D#21 H_D#22 H_D#23 H_D#24 H_D#25 H_D#26 H_D#27 H_D#28 H_D#29 H_D#30 H_D#31 <7> <7> <7> R21 R22 H_DSTBN#1 H_DSTBP#1 H_DINV#1
E22 F24 E26 G22 F23 G25 E25 E23 K24 G24 J24 J23 H22 F26 K22 H23 J26 H26 H25 N22 K25 P26 R23 L23 M24 L22 M23 P25 P23 P22 T24 R24 L25 T25 N25 L26 M26 N24 AD26 C23 D25 C24 AF26 AF1 A26 C3 B22 B23 C21
D[0]# D[1]# D[2]# D[3]# D[4]# D[5]# D[6]# D[7]# D[8]# D[9]# D[10]# D[11]# D[12]# D[13]# D[14]# D[15]# DSTBN[0]# DSTBP[0]# DINV[0]# D[16]# D[17]# D[18]# D[19]# D[20]# D[21]# D[22]# D[23]# D[24]# D[25]# D[26]# D[27]# D[28]# D[29]# D[30]# D[31]# DSTBN[1]# DSTBP[1]# DINV[1]# GTLREF TEST1 TEST2 TEST3 TEST4 TEST5 TEST6 TEST7 BSEL[0] BSEL[1] BSEL[2]
Penryn
D[32]# D[33]# D[34]# D[35]# D[36]# D[37]# D[38]# D[39]# D[40]# D[41]# D[42]# D[43]# D[44]# D[45]# D[46]# D[47]# DSTBN[2]# DSTBP[2]# DINV[2]# D[48]# D[49]# D[50]# D[51]# D[52]# D[53]# D[54]# D[55]# D[56]# D[57]# D[58]# D[59]# D[60]# D[61]# D[62]# D[63]# DSTBN[3]# DSTBP[3]# DINV[3]# COMP[0] COMP[1] COMP[2] COMP[3]
Y22 AB24 V24 V26 V23 T22 U25 U23 Y25 W22 Y23 W24 W25 AA23 AA24 AB25 Y26 AA26 U22 AE24 AD24 AA21 AB22 AB21 AC26 AD20 AE22 AF23 AC25 AE21 AD21 AC22 AD23 AF22 AC23 AE25 AF24 AC20 R26 U26 AA1 Y1 E5 B5 D24 D6 D7 AE6
H_D#32 H_D#33 H_D#34 H_D#35 H_D#36 H_D#37 H_D#38 H_D#39 H_D#40 H_D#41 H_D#42 H_D#43 H_D#44 H_D#45 H_D#46 H_D#47 H_DSTBN#2 <7> H_DSTBP#2 <7> H_DINV#2 <7> H_D#48 H_D#49 H_D#50 H_D#51 H_D#52 H_D#53 H_D#54 H_D#55 H_D#56 H_D#57 H_D#58 H_D#59 H_D#60 H_D#61 H_D#62 H_D#63 H_DSTBN#3 <7> H_DSTBP#3 <7> H_DINV#3 <7> COMP0 COMP1 COMP2 COMP3 R26 R25 R24 R23
C
+1.05VS
R27 1K_0402_1%
Trace Close CPU < 0.5' Width=4 mil , Spacing: 15mil (55Ohm)
2
2 2
C1477 1
@ @ @
R29 2K_0402_1%
2
1 1 T1
T2
GTL_REF0 1K_0402_5% TEST1 1K_0402_5% TEST2 TEST3 @ PAD 0.1U_0402_16V4Z TEST4 TEST5 @ PAD
MISC
1 1 1 1
2 2 2 2
27.4_0402_1% 54.9_0402_1% 27.4_0402_1% 54.9_0402_1%
<16> CPU_BSEL0 <16> CPU_BSEL1 <16> CPU_BSEL2
DPRSTP# DPSLP# DPWR# PWRGOOD SLP# PSI#
H_PWRGOOD H_CPUSLP#
H_DPRSTP# <8,26,50> H_DPSLP# <26> H_DPWR# <7> H_PWRGOOD <26> H_CPUSLP# <7> PSI# <50>
CONN@
TRACE CLOSELY CPU < 0.5'
B
COMP0, COMP2 layout : Width 18mils and Space 25mils (27.4Ohms) COMP1, COMP3 layout : Width 4mils and Space 25mils (55Ohms)
A7 A9 A10 A12 A13 A15 A17 A18 A20 B7 B9 B10 B12 B14 B15 B17 B18 B20 C9 C10 C12 C13 C15 C17 C18 D9 D10 D12 D14 D15 D17 D18 E7 E9 E10 E12 E13 E15 E17 E18 E20 F7 F9 F10 F12 F14 F15 F17 F18 F20 AA7 AA9 AA10 AA12 AA13 AA15 AA17 AA18 AA20 AB9 AC10 AB10 AB12 AB14 AB15 AB17 AB18
VCC[001] VCC[002] VCC[003] VCC[004] VCC[005] VCC[006] VCC[007] VCC[008] VCC[009] VCC[010] VCC[011] VCC[012] VCC[013] VCC[014] VCC[015] VCC[016] VCC[017] VCC[018] VCC[019] VCC[020] VCC[021] VCC[022] VCC[023] VCC[024] VCC[025] VCC[026] VCC[027] VCC[028] VCC[029] VCC[030] VCC[031] VCC[032] VCC[033] VCC[034] VCC[035] VCC[036] VCC[037] VCC[038] VCC[039] VCC[040] VCC[041] VCC[042] VCC[043] VCC[044] VCC[045] VCC[046] VCC[047] VCC[048] VCC[049] VCC[050] VCC[051] VCC[052] VCC[053] VCC[054] VCC[055] VCC[056] VCC[057] VCC[058] VCC[059] VCC[060] VCC[061] VCC[062] VCC[063] VCC[064] VCC[065] VCC[066] VCC[067]
Penryn
DATA GRP 3
VCC[068] VCC[069] VCC[070] VCC[071] VCC[072] VCC[073] VCC[074] VCC[075] VCC[076] VCC[077] VCC[078] VCC[079] VCC[080] VCC[081] VCC[082] VCC[083] VCC[084] VCC[085] VCC[086] VCC[087] VCC[088] VCC[089] VCC[090] VCC[091] VCC[092] VCC[093] VCC[094] VCC[095] VCC[096] VCC[097] VCC[098] VCC[099] VCC[100] VCCP[01] VCCP[02] VCCP[03] VCCP[04] VCCP[05] VCCP[06] VCCP[07] VCCP[08] VCCP[09] VCCP[10] VCCP[11] VCCP[12] VCCP[13] VCCP[14] VCCP[15] VCCP[16] VCCA[01] VCCA[02] VID[0] VID[1] VID[2] VID[3] VID[4] VID[5] VID[6] VCCSENSE VSSSENSE
.
AB20 AB7 AC7 AC9 AC12 AC13 AC15 AC17 AC18 AD7 AD9 AD10 AD12 AD14 AD15 AD17 AD18 AE9 AE10 AE12 AE13 AE15 AE17 AE18 AE20 AF9 AF10 AF12 AF14 AF15 AF17 AF18 AF20 G21 V6 J6 K6 M6 J21 K21 M21 N21 N6 R21 R6 T21 T6 V21 W21 B26 C26
+CPU_CORE
D
DATA GRP 2
DATA GRP 0 DATA GRP 1
C
+1.05VS
1
2
20mils
+1.5VS CPU_VID0 CPU_VID1 CPU_VID2 CPU_VID3 CPU_VID4 CPU_VID5 CPU_VID6 1 R28 VCCSENSE VSSSENSE R30 C7 C8 <50> <50> 0.01U_0402_16V7K <50> 2 2 <50> <50> 10U_0805_10V4Z <50> <50>
1
1
1
AD6 AF5 AE5 AF4 AE3 AF3 AE2 AF7 AE7
2 100_0402_1%
+CPU_CORE
B
VCCSENSE <50> VSSSENSE <50>
CONN@
1
2 100_0402_1%
A
A
Security Classification Issued Date 2008/11/24
Compal Secret Data
Deciphered Date 2009/12/31
Title
Compal Electronics, Inc. SCHEMATIC LA-4493
Document Number Rev D Sheet
1
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL Size AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D B DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
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JCPU1D
D
C
B
A4 A8 A11 A14 A16 A19 A23 AF2 B6 B8 B11 B13 B16 B19 B21 B24 C5 C8 C11 C14 C16 C19 C2 C22 C25 D1 D4 D8 D11 D13 D16 D19 D23 D26 E3 E6 E8 E11 E14 E16 E19 E21 E24 F5 F8 F11 F13 F16 F19 F2 F22 F25 G4 G1 G23 G26 H3 H6 H21 H24 J2 J5 J22 J25 K1 K4 K23 K26 L3 L6 L21 L24 M2 M5 M22 M25 N1 N4 N23 N26 P3
VSS[001] VSS[002] VSS[003] VSS[004] VSS[005] VSS[006] VSS[007] VSS[008] VSS[009] VSS[010] VSS[011] VSS[012] VSS[013] VSS[014] VSS[015] VSS[016] VSS[017] VSS[018] VSS[019] VSS[020] VSS[021] VSS[022] VSS[023] VSS[024] VSS[025] VSS[026] VSS[027] VSS[028] VSS[029] VSS[030] VSS[031] VSS[032] VSS[033] VSS[034] VSS[035] VSS[036] VSS[037] VSS[038] VSS[039] VSS[040] VSS[041] VSS[042] VSS[043] VSS[044] VSS[045] VSS[046] VSS[047] VSS[048] VSS[049] VSS[050] VSS[051] VSS[052] VSS[053] VSS[054] VSS[055] VSS[056] VSS[057] VSS[058] VSS[059] VSS[060] VSS[061] VSS[062] VSS[063] VSS[064] VSS[065] VSS[066] VSS[067] VSS[068] VSS[069] VSS[070] VSS[071] VSS[072] VSS[073] VSS[074] VSS[075] VSS[076] VSS[077] VSS[078] VSS[079] VSS[080] VSS[081]
Penryn
VSS[082] VSS[083] VSS[084] VSS[085] VSS[086] VSS[087] VSS[088] VSS[089] VSS[090] VSS[091] VSS[092] VSS[093] VSS[094] VSS[095] VSS[096] VSS[097] VSS[098] VSS[099] VSS[100] VSS[101] VSS[102] VSS[103] VSS[104] VSS[105] VSS[106] VSS[107] VSS[108] VSS[109] VSS[110] VSS[111] VSS[112] VSS[113] VSS[114] VSS[115] VSS[116] VSS[117] VSS[118] VSS[119] VSS[120] VSS[121] VSS[122] VSS[123] VSS[124] VSS[125] VSS[126] VSS[127] VSS[128] VSS[129] VSS[130] VSS[131] VSS[132] VSS[133] VSS[134] VSS[135] VSS[136] VSS[137] VSS[138] VSS[139] VSS[140] VSS[141] VSS[142] VSS[143] VSS[144] VSS[145] VSS[146] VSS[147] VSS[148] VSS[149] VSS[150] VSS[151] VSS[152] VSS[153] VSS[154] VSS[155] VSS[156] VSS[157] VSS[158] VSS[159] VSS[160] VSS[161] VSS[162] VSS[163]
.
P6 P21 P24 R2 R5 R22 R25 T1 T4 T23 T26 U3 U6 U21 U24 V2 V5 V22 V25 W1 W4 W23 W26 Y3 Y6 Y21 Y24 AA2 AA5 AA8 AA11 AA14 AA16 AA19 AA22 AA25 AB1 AB4 AB8 AB11 AB13 AB16 AB19 AB23 AB26 AC3 AC6 AC8 AC11 AC14 AC16 AC19 AC21 AC24 AD2 AD5 AD8 AD11 AD13 AD16 AD19 AD22 AD25 AE1 AE4 AE8 AE11 AE14 AE16 AE19 AE23 AE26 A2 AF6 AF8 AF11 AF13 AF16 AF19 AF21 A25 AF25
+CPU_CORE
D
1 2
+ C55 900P_PFAF250E128MNTTE_2.5VM
3 4
+CPU_CORE
C
10U_0805_6.3V6M
10U_0805_6.3V6M
10U_0805_6.3V6M
10U_0805_6.3V6M
10U_0805_6.3V6M
10U_0805_6.3V6M
10U_0805_6.3V6M
1
C416
1
C425
1
C426
1
C427
1
C428
1
C429
1
10U_0805_6.3V6M
C430
1
C431
2
2
2
2
2
2
2
2
B
+CPU-CORE Decoupling SPCAP,Polymer MLCC 0805 X5R
C,uF 4X330uF 32X22uF 32X10uF
ESR, mohm 6m ohm/4 3m ohm/32 3m ohm/32
ESL,nH 1.8nH/6 0.6nH/32 0.6nH/32
+1.05VS 330U_D2E_2.5VM_R15
CONN@
0.1U_0402_16V4Z
0.1U_0402_16V4Z
0.1U_0402_16V4Z
0.1U_0402_16V4Z
0.1U_0402_16V4Z
+ C1478
1
C45
1 C46 2
1
C47
1
C48
1
0.1U_0402_16V4Z
1
C49
1
C50
2
2
2
2
2
2
A
A
Security Classification Issued Date 2008/11/24
Compal Secret Data
Deciphered Date 2009/12/31
Title
Compal Electronics, Inc. SCHEMATIC LA-4493
Document Number Rev D Sheet
1
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL Size AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D B DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
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<5>
H_D#[0..63] H_D#0 H_D#1 H_D#2 H_D#3 H_D#4 H_D#5 H_D#6 H_D#7 H_D#8 H_D#9 H_D#10 H_D#11 H_D#12 H_D#13 H_D#14 H_D#15 H_D#16 H_D#17 H_D#18 H_D#19 H_D#20 H_D#21 H_D#22 H_D#23 H_D#24 H_D#25 H_D#26 H_D#27 H_D#28 H_D#29 H_D#30 H_D#31 H_D#32 H_D#33 H_D#34 H_D#35 H_D#36 H_D#37 H_D#38 H_D#39 H_D#40 H_D#41 H_D#42 H_D#43 H_D#44 H_D#45 H_D#46 H_D#47 H_D#48 H_D#49 H_D#50 H_D#51 H_D#52 H_D#53 H_D#54 H_D#55 H_D#56 H_D#57 H_D#58 H_D#59 H_D#60 H_D#61 H_D#62 H_D#63 H_SWING H_RCOMP
U2A
H_A#[3..35]
<4>
D
+1.05VS
R47 221_0402_1%
H_SWING
width=10mil
1
C59 0.1U_0402_16V4Z
C
R55 100_0402_1%
H_RCOMP
width=10mil
R54 24.9_0402_1%
2
1
HOST
2 1
B
F2 G8 F8 E6 G2 H6 H2 F6 D4 H3 M9 M11 J1 J2 N12 J6 P2 L2 R2 N9 L6 M5 J3 N2 R1 N5 N6 P13 N8 L7 N10 M3 Y3 AD14 Y6 Y10 Y12 Y14 Y7 W2 AA8 Y9 AA13 AA9 AA11 AD11 AD10 AD13 AE12 AE9 AA2 AD8 AA3 AD3 AD7 AE14 AF3 AC1 AE3 AC3 AE11 AE8 AG2 AD6 C5 E3
H_D#_0 H_D#_1 H_D#_2 H_D#_3 H_D#_4 H_D#_5 H_D#_6 H_D#_7 H_D#_8 H_D#_9 H_D#_10 H_D#_11 H_D#_12 H_D#_13 H_D#_14 H_D#_15 H_D#_16 H_D#_17 H_D#_18 H_D#_19 H_D#_20 H_D#_21 H_D#_22 H_D#_23 H_D#_24 H_D#_25 H_D#_26 H_D#_27 H_D#_28 H_D#_29 H_D#_30 H_D#_31 H_D#_32 H_D#_33 H_D#_34 H_D#_35 H_D#_36 H_D#_37 H_D#_38 H_D#_39 H_D#_40 H_D#_41 H_D#_42 H_D#_43 H_D#_44 H_D#_45 H_D#_46 H_D#_47 H_D#_48 H_D#_49 H_D#_50 H_D#_51 H_D#_52 H_D#_53 H_D#_54 H_D#_55 H_D#_56 H_D#_57 H_D#_58 H_D#_59 H_D#_60 H_D#_61 H_D#_62 H_D#_63 H_SWING H_RCOMP
H_A#_3 H_A#_4 H_A#_5 H_A#_6 H_A#_7 H_A#_8 H_A#_9 H_A#_10 H_A#_11 H_A#_12 H_A#_13 H_A#_14 H_A#_15 H_A#_16 H_A#_17 H_A#_18 H_A#_19 H_A#_20 H_A#_21 H_A#_22 H_A#_23 H_A#_24 H_A#_25 H_A#_26 H_A#_27 H_A#_28 H_A#_29 H_A#_30 H_A#_31 H_A#_32 H_A#_33 H_A#_34 H_A#_35 H_ADS# H_ADSTB#_0 H_ADSTB#_1 H_BNR# H_BPRI# H_BREQ# H_DEFER# H_DBSY# HPLL_CLK HPLL_CLK# H_DPWR# H_DRDY# H_HIT# H_HITM# H_LOCK# H_TRDY#
A14 C15 F16 H13 C18 M16 J13 P16 R16 N17 M13 E17 P17 F17 G20 B19 J16 E20 H16 J20 L17 A17 B17 L16 C21 J17 H20 B18 K17 B20 F21 K21 L20 H12 B16 G17 A9 F11 G12 E9 B10 AH7 AH6 J11 F9 H9 E12 H11 C9
H_A#3 H_A#4 H_A#5 H_A#6 H_A#7 H_A#8 H_A#9 H_A#10 H_A#11 H_A#12 H_A#13 H_A#14 H_A#15 H_A#16 H_A#17 H_A#18 H_A#19 H_A#20 H_A#21 H_A#22 H_A#23 H_A#24 H_A#25 H_A#26 H_A#27 H_A#28 H_A#29 H_A#30 H_A#31 H_A#32 H_A#33 H_A#34 H_A#35 H_ADS# H_ADSTB#0 H_ADSTB#1 H_BNR# H_BPRI# H_BR0# H_DEFER# H_DBSY# CLK_MCH_BCLK CLK_MCH_BCLK# H_DPWR# H_DRDY# H_HIT# H_HITM# H_LOCK# H_TRDY# H_ADS# <4> H_ADSTB#0 <4> H_ADSTB#1 <4> H_BNR# <4> H_BPRI# <4> H_BR0# <4> H_DEFER# <4> H_DBSY# <4> CLK_MCH_BCLK <16> CLK_MCH_BCLK# <16> H_DPWR# <5> H_DRDY# <4> H_HIT# <4> H_HITM# <4> H_LOCK# <4> H_TRDY# <4>
D
2
2
1
C
H_DINV#_0 H_DINV#_1 H_DINV#_2 H_DINV#_3 H_DSTBN#_0 H_DSTBN#_1 H_DSTBN#_2 H_DSTBN#_3 H_DSTBP#_0 H_DSTBP#_1 H_DSTBP#_2 H_DSTBP#_3 H_REQ#_0 H_REQ#_1 H_REQ#_2 H_REQ#_3 H_REQ#_4 H_RS#_0 H_RS#_1 H_RS#_2
GM45@
J8 L3 Y13 Y1 L10 M7 AA5 AE6 L9 M8 AA6 AE5 B15 K13 F13 B13 B14 B6 F12 C8
H_DINV#0 H_DINV#1 H_DINV#2 H_DINV#3 H_DSTBN#0 H_DSTBN#1 H_DSTBN#2 H_DSTBN#3 H_DSTBP#0 H_DSTBP#1 H_DSTBP#2 H_DSTBP#3 H_REQ#0 H_REQ#1 H_REQ#2 H_REQ#3 H_REQ#4 H_RS#0 H_RS#1 H_RS#2
H_DINV#0 H_DINV#1 H_DINV#2 H_DINV#3 H_DSTBN#0 H_DSTBN#1 H_DSTBN#2 H_DSTBN#3 <5> <5> <5> <5>
<5> <5> <5> <5>
B
+1.05VS
H_DSTBP#0 <5> H_DSTBP#1 <5> H_DSTBP#2 <5> H_DSTBP#3 <5> H_REQ#[0..4]
<4>
2
R46 1K_0402_1%
<4> H_RESET# <5> H_CPUSLP#
H_RESET# H_CPUSLP# H_AVREF
C12 E11 A11 B11
H_CPURST# H_CPUSLP# H_AVREF H_DVREF
H_RS#[0..2]
<4>
width:spacing=10mil:20mil (<0.5")
1 1
R52 2K_0402_1% C58 @ 0.1U_0402_16V4Z
1
CANTIGA ES_FCBGA1329
2
2
within 100mil to Ball A11,B11
A
A
Security Classification Issued Date 2008/11/24
Compal Secret Data
Deciphered Date 2009/12/31
Title
Compal Electronics, Inc. SCHEMATIC LA-4493
Document Number Rev D Sheet
1
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL Size AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D B DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
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DDR3
U2B M36 N36 R33 T33 AH9 AH10 AH12 AH13 K12 AL34 AK34 AN35 AM35 T24 RSVD1 RSVD2 RSVD3 RSVD4 RSVD5 RSVD6 RSVD7 RSVD8 RSVD9 RSVD10 RSVD11 RSVD12 RSVD13 RSVD14 SA_CK_0 SA_CK_1 SB_CK_0 SB_CK_1 SA_CK#_0 SA_CK#_1 SB_CK#_0 SB_CK#_1 SA_CKE_0 SA_CKE_1 SB_CKE_0 SB_CKE_1 SA_CS#_0 SA_CS#_1 SB_CS#_0 SB_CS#_1 SA_ODT_0 SA_ODT_1 SB_ODT_O SB_ODT_1 SM_RCOMP SM_RCOMP# SM_RCOMP_VOH SM_RCOMP_VOL SM_VREF SM_PWROK SM_REXT SM_DRAMRST# DPLL_REF_CLK DPLL_REF_CLK# DPLL_REF_SSCLK DPLL_REF_SSCLK# PEG_CLK PEG_CLK# AP24 AT21 AV24 AU20 AR24 AR21 AU24 AV20 BC28 AY28 AY36 BB36 BA17 AY16 AV16 AR13 BD17 AY17 BF15 AY13 BG22 BH21 BF28 BH28 AV42 AR36 BF17 BC36 B38 A38 E41 F41 F43 E43 M_CLK_DDR0 M_CLK_DDR1 M_CLK_DDR2 M_CLK_DDR3 M_CLK_DDR#0 M_CLK_DDR#1 M_CLK_DDR#2 M_CLK_DDR#3 DDR_CKE0_DIMMA DDR_CKE1_DIMMA DDR_CKE2_DIMMB DDR_CKE3_DIMMB DDR_CS0_DIMMA# DDR_CS1_DIMMA# DDR_CS2_DIMMB# DDR_CS3_DIMMB# M_ODT0 M_ODT1 M_ODT2 M_ODT3 SMRCOMP SMRCOMP# SM_RCOMP_VOH SM_RCOMP_VOL SM_VREF DDR3_SM_PWROK SM_REXT R37 SM_DRAMRST# 1 R34 R35 1 1 M_CLK_DDR0 M_CLK_DDR1 M_CLK_DDR2 M_CLK_DDR3 M_CLK_DDR#0 M_CLK_DDR#1 M_CLK_DDR#2 M_CLK_DDR#3 <14> <14> <15> <15> <14> <14> <15> <15> <14> <14> <15> <15> <14> <14> <15> <15> +1.5V 1
DDR3
COMPENSATION
R31 1K_0402_1% 2 SM_RCOMP_VOH 1 C52 2 2.2U_0603_6.3V6K 1 C51 2 0.01U_0402_16V7K
D
All RSVD balls on GMCH should be left No Connect.
B31 B2 M1 AY21
DDR_CKE0_DIMMA DDR_CKE1_DIMMA DDR_CKE2_DIMMB DDR_CKE3_DIMMB DDR_CS0_DIMMA# DDR_CS1_DIMMA# DDR_CS2_DIMMB# DDR_CS3_DIMMB# M_ODT0 M_ODT1 M_ODT2 M_ODT3 <14> <14> <15> <15>
R32
2 1 3.01K_0402_1%
SM_DRAMRST# would be needed for DDR3 only For Cantiga 80 Ohm
D
SM_RCOMP_VOL 2 1 1K_0402_1% R33 C54 1 C53 1 0.01U_0402_16V7K 2.2U_0603_6.3V6K
DDR CLK/ CONTROL/
RSVD15 RSVD16 RSVD17 RSVD20
BG23 BF23 BH18 BF18
RSVD22 RSVD23 RSVD24 RSVD25
2
1
DDR3
1
2
1
CLK
RSVD
DDR3
+1.5V +1.5V R45 1K_0402_1% @ 1 R1135 R48 1K_0402_1%
2
2
2 80.6_0402_1% 2 80.6_0402_1%
20mil
DDR3
CLK_DREF_96M CLK_DREF_96M# CLK_DREF_SSC CLK_DREF_SSC# CLK_MCH_3GPLL CLK_MCH_3GPLL#
DDR3_SM_PWROK <38> 2 499_0402_1% SM_DRAMRST# <14,15> CLK_DREF_96M <16> CLK_DREF_96M# <16> CLK_DREF_SSC <16> CLK_DREF_SSC# <16> CLK_MCH_3GPLL <16> CLK_MCH_3GPLL# <16>
2 +V_DDR3_DIMM_REF 0_0402_5%
CLK_DREF_96M CLK_DREF_96M# CLK_DREF_SSC CLK_DREF_SSC#
R1134 1 PM@ R1136 1 PM@ R1137 1 PM@ R1138 1 PM@
2 2 2 2
0_0402_5% 0_0402_5% 0_0402_5% 0_0402_5%
C57 0.1U_0402_16V4Z 2
as close as possible to the related balls
C
Strap Pin Table
CFG[2:0] CFG5 CFG6 CFG9 CFG10 CFG[13:12]
011 = FSB667 010 = FSB800 000 = FSB1067
C
DMI_RXN_0 DMI_RXN_1 DMI_RXN_2 DMI_RXN_3 <16> MCH_CLKSEL0 <16> MCH_CLKSEL1 <16> MCH_CLKSEL2 +3VS 1 R38 1 R39 1 R40 2 PM_EXTTS#0 10K_0402_5% 2 PM_EXTTS#1 10K_0402_5% 2 MCH_CLKREQ# 10K_0402_5% MCH_CLKSEL0 MCH_CLKSEL1 MCH_CLKSEL2 MCH_CFG_5 MCH_CFG_6 MCH_CFG_7 MCH_CFG_9 MCH_CFG_10 MCH_CFG_12 MCH_CFG_13 MCH_CFG_16 MCH_CFG_19 MCH_CFG_20
B
AE41 AE37 AE47 AH39 AE40 AE38 AE48 AH40 AE35 AE43 AE46 AH42 AD35 AE44 AF46 AH43
DMI_ITX_MRX_N0 DMI_ITX_MRX_N1 DMI_ITX_MRX_N2 DMI_ITX_MRX_N3 DMI_ITX_MRX_P0 DMI_ITX_MRX_P1 DMI_ITX_MRX_P2 DMI_ITX_MRX_P3 DMI_MTX_IRX_N0 DMI_MTX_IRX_N1 DMI_MTX_IRX_N2 DMI_MTX_IRX_N3 DMI_MTX_IRX_P0 DMI_MTX_IRX_P1 DMI_MTX_IRX_P2 DMI_MTX_IRX_P3
DMI_ITX_MRX_N0 DMI_ITX_MRX_N1 DMI_ITX_MRX_N2 DMI_ITX_MRX_N3 DMI_ITX_MRX_P0 DMI_ITX_MRX_P1 DMI_ITX_MRX_P2 DMI_ITX_MRX_P3 DMI_MTX_IRX_N0 DMI_MTX_IRX_N1 DMI_MTX_IRX_N2 DMI_MTX_IRX_N3 DMI_MTX_IRX_P0 DMI_MTX_IRX_P1 DMI_MTX_IRX_P2 DMI_MTX_IRX_P3
<27> <27> <27> <27> <27> <27> <27> <27> <27> <27> <27> <27> <27> <27> <27> <27>
Use VGATE for GMCH_PWROK
<16,27,50> VGATE <27> ICH_PWROK @ 1 R1139 ICH_PWROK 1 R1140 VGATE GMCH_PWROK 2 0_0402_5% 2 0_0402_5%
GRAPHICS VID
T25 R25 P25 P20 P24 C25 N24 M24 E21 C23 C24 N21 P21 T21 R20 M20 L21 H21 P29 R28 T28
CFG_0 CFG_1 CFG_2 CFG_3 CFG_4 CFG_5 CFG_6 CFG_7 CFG_8 CFG_9 CFG_10 CFG_11 CFG_12 CFG_13 CFG_14 CFG_15 CFG_16 CFG_17 CFG_18 CFG_19 CFG_20
DMI_RXP_0 DMI_RXP_1 DMI_RXP_2 DMI_RXP_3
0 = DMI x 2 1 = DMI x 4
* (Default) *(Default)
0 = iTPM Host Interface is enabled
DMI
DMI_TXN_0 DMI_TXN_1 DMI_TXN_2 DMI_TXN_3 DMI_TXP_0 DMI_TXP_1 DMI_TXP_2 DMI_TXP_3
1 = iTPM Host Interface is Disabled 0 = Lane Reversal Enable 1 = Normal Operation * (Default)
0 = PCIe Loopback Enable 1 = Disable * (Default) 00 01 10 11 = Reserved = XOR Mode Enabled = All Z Mode Enabled = Normal Operation *
CFG
(Default)
CFG16 CFG19
GFX_VID_0 GFX_VID_1 GFX_VID_2 GFX_VID_3 GFX_VID_4 B33 B32 G33 F33 E33
CFG20 (PCIE/SDVO select) SDVO_CTRLDATA
<27> PM_SYNC# <5,26,50> H_DPRSTP# <14> PM_EXTTS#0 <15> PM_EXTTS#1 <17,25,27,31,32,36> PLT_RST# <4,26> H_THERMTRIP# <27,50> PM_DPRSLPVR
R1141 1 R1142 1
R1143 1 R1144 1 R1145 1
PM_SYNC#_R PM_DPRSTP#_R PM_EXTTS#0 PM_EXTTS#1 GMCH_PWROK 2 100_0402_5% MCH_RSTIN# THERMTRIP#_R 2 0_0402_5% DPRSLPVR_R 0_0402_5% 2 2 0_0402_5% 2 0_0402_5%
R29 B7 N33 P32 AT40 AT11 T20 R32 BG48 BF48 BD48 BC48 BH47 BG47 BE47 BH46 BF46 BG45 BH44 BH43 BH6 BH5 BG4 BH3 BF3 BH2 BG2 BE2 BG1 BF1 BD1 BC1 F1 A47
0 = Dynamic ODT Disabled 1 = Dynamic ODT Enabled * (Default) 0 = Normal Operation *(Default) 1 = DMI Lane Reversal Enable 0 = Only PCIE or SDVO is operational. * (Default) 1 = PCIE/SDVO are operating simu. 0 = No SDVO Card Present * (Default) 1 = SDVO Card Present 0 = LFP Disable * (Default) 1 = LFP Card Present; PCIE disable
0 = Digital DisplayPort Disable * (Default) 1 = Digital DisplayPort Device Present
B
PM_SYNC# PM_DPRSTP# PM_EXT_TS#_0 PM_EXT_TS#_1 PWROK RSTIN# THERMTRIP# DPRSLPVR NC_1 NC_2 NC_3 NC_4 NC_5 NC_6 NC_7 NC_8 NC_9 NC_10 NC_11 NC_12 NC_13 NC_14 NC_15 NC_16 NC_17 NC_18 NC_19 NC_20 NC_21 NC_22 NC_23 NC_24 NC_25 NC_26
2
CL_CLK CL_DATA CL_PWROK CL_RST# CL_VREF DDPC_CTRLCLK DDPC_CTRLDATA SDVO_CTRLCLK SDVO_CTRLDATA CLKREQ# ICH_SYNC# TSATN#
AH37 AH36 AN36 AJ35 AH34 N28 M28 G36 E36 K36 H36 B12
ME
ICH_PWROK CL_VREF
CL_CLK0 <27> CL_DATA0 <27> CL_RST#0 <27> 1
1K_0402_1%
2
0.1U_0402_16V4Z
2
1
+3VS +3VS +1.05VS 1 1 1
MISC
SDVO_SCLK SDVO_SDATA MCH_CLKREQ#
511_0402_1%
PM NC
GFX_VR_EN
C34 +1.05VS R43
L_DDC_DATA DDPC_CTRLDATA
MCH_CFG_5 MCH_CFG_6 MCH_CFG_7 MCH_CFG_9 MCH_CFG_10 MCH_CFG_12 MCH_CFG_13 MCH_CFG_16
C56 SDVO_SCLK <30> SDVO_SDATA <30> MCH_CLKREQ# <16> MCH_ICH_SYNC# <27>
1
R44
R1147 1K_0402_5% R1148 1K_0402_5% 2
MCH_TSATN#
MCH_TSATN_EC# <36> 1 C Q75 MMBT3904_SOT23-3
2 R1146 2 R79 2 R81 2 R84 2 R86 2 R77 2 R78 2 R1149
@ @ @ @ @ @ @ @
1 2.21K_0402_1% 1 4.02K_0402_1% 1 2.21K_0402_1% 1 2.21K_0402_1% 1 2.21K_0402_1% 1 2.21K_0402_1% 1 2.21K_0402_1% 1 2.21K_0402_1%
A
A
R1150 54.9_0402_1% R1152 2 MCH_TSATN# 1 2 2 B
1
2 B 3 E
HDA
C
3
330_0402_5%
E
Q76 MMBT3904_SOT23-3
HDA_BCLK HDA_RST# HDA_SDI HDA_SDO HDA_SYNC
B28 B30 B29 C29 A28
HDA_BITCLK_MCH HDA_RST_MCH# HDA_SDIN2_MCH HDA_SDOUT_MCH HDA_SYNC_MCH
HDA_BITCLK_MCH <26> HDA_RST_MCH# <26> GM@ 2 1 R1151 33_0402_5% HDA_SDOUT_MCH <26> HDA_SYNC_MCH <26>
2
HDA_SDIN2 <26>
MCH_CFG_19 R73 MCH_CFG_20 R75
2 @ 2 @
Notice: Please check HDA power rail to select HDA controller. Security Classification Issued Date 2008/11/24
1 4.02K_0402_1% 1 4.02K_0402_1%
+3VS
CANTIGA ES_FCBGA1329
GM45@
Compal Secret Data
Deciphered Date 2009/12/31
Title
Compal Electronics, Inc. SCHEMATIC LA-4493
Rev D Sheet
1
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL Size Document Number AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS Custom MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
401689
Date:
Thursday, March 19, 2009
8
of
54
5
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2

5
4
3
2
1
D
D
<15> DDR_B_D[0..63] <14> DDR_A_D[0..63] DDR_A_D0 DDR_A_D1 DDR_A_D2 DDR_A_D3 DDR_A_D4 DDR_A_D5 DDR_A_D6 DDR_A_D7 DDR_A_D8 DDR_A_D9 DDR_A_D10 DDR_A_D11 DDR_A_D12 DDR_A_D13 DDR_A_D14 DDR_A_D15 DDR_A_D16 DDR_A_D17 DDR_A_D18 DDR_A_D19 DDR_A_D20 DDR_A_D21 DDR_A_D22 DDR_A_D23 DDR_A_D24 DDR_A_D25 DDR_A_D26 DDR_A_D27 DDR_A_D28 DDR_A_D29 DDR_A_D30 DDR_A_D31 DDR_A_D32 DDR_A_D33 DDR_A_D34 DDR_A_D35 DDR_A_D36 DDR_A_D37 DDR_A_D38 DDR_A_D39 DDR_A_D40 DDR_A_D41 DDR_A_D42 DDR_A_D43 DDR_A_D44 DDR_A_D45 DDR_A_D46 DDR_A_D47 DDR_A_D48 DDR_A_D49 DDR_A_D50 DDR_A_D51 DDR_A_D52 DDR_A_D53 DDR_A_D54 DDR_A_D55 DDR_A_D56 DDR_A_D57 DDR_A_D58 DDR_A_D59 DDR_A_D60 DDR_A_D61 DDR_A_D62 DDR_A_D63 AJ38 AJ41 AN38 AM38 AJ36 AJ40 AM44 AM42 AN43 AN44 AU40 AT38 AN41 AN39 AU44 AU42 AV39 AY44 BA40 BD43 AV41 AY43 BB41 BC40 AY37 BD38 AV37 AT36 AY38 BB38 AV36 AW36 BD13 AU11 BC11 BA12 AU13 AV13 BD12 BC12 BB9 BA9 AU10 AV9 BA11 BD9 AY8 BA6 AV5 AV7 AT9 AN8 AU5 AU6 AT5 AN10 AM11 AM5 AJ9 AJ8 AN12 AM13 AJ11 AJ12 U2E U2D SA_DQ_0 SA_DQ_1 SA_DQ_2 SA_DQ_3 SA_DQ_4 SA_DQ_5 SA_DQ_6 SA_DQ_7 SA_DQ_8 SA_DQ_9 SA_DQ_10 SA_DQ_11 SA_DQ_12 SA_DQ_13 SA_DQ_14 SA_DQ_15 SA_DQ_16 SA_DQ_17 SA_DQ_18 SA_DQ_19 SA_DQ_20 SA_DQ_21 SA_DQ_22 SA_DQ_23 SA_DQ_24 SA_DQ_25 SA_DQ_26 SA_DQ_27 SA_DQ_28 SA_DQ_29 SA_DQ_30 SA_DQ_31 SA_DQ_32 SA_DQ_33 SA_DQ_34 SA_DQ_35 SA_DQ_36 SA_DQ_37 SA_DQ_38 SA_DQ_39 SA_DQ_40 SA_DQ_41 SA_DQ_42 SA_DQ_43 SA_DQ_44 SA_DQ_45 SA_DQ_46 SA_DQ_47 SA_DQ_48 SA_DQ_49 SA_DQ_50 SA_DQ_51 SA_DQ_52 SA_DQ_53 SA_DQ_54 SA_DQ_55 SA_DQ_56 SA_DQ_57 SA_DQ_58 SA_DQ_59 SA_DQ_60 SA_DQ_61 SA_DQ_62 SA_DQ_63 SA_BS_0 SA_BS_1 SA_BS_2 SA_RAS# SA_CAS# SA_WE# BD21 BG18 AT25 BB20 BD20 AY20 DDR_A_BS0 DDR_A_BS1 DDR_A_BS2 DDR_A_RAS# DDR_A_CAS# DDR_A_WE# DDR_A_BS0 DDR_A_BS1 DDR_A_BS2 <14> <14> <14> DDR_B_D0 DDR_B_D1 DDR_B_D2 DDR_B_D3 DDR_B_D4 DDR_B_D5 DDR_B_D6 DDR_B_D7 DDR_B_D8 DDR_B_D9 DDR_B_D10 DDR_B_D11 DDR_B_D12 DDR_B_D13 DDR_B_D14 DDR_B_D15 DDR_B_D16 DDR_B_D17 DDR_B_D18 DDR_B_D19 DDR_B_D20 DDR_B_D21 DDR_B_D22 DDR_B_D23 DDR_B_D24 DDR_B_D25 DDR_B_D26 DDR_B_D27 DDR_B_D28 DDR_B_D29 DDR_B_D30 DDR_B_D31 DDR_B_D32 DDR_B_D33 DDR_B_D34 DDR_B_D35 DDR_B_D36 DDR_B_D37 DDR_B_D38 DDR_B_D39 DDR_B_D40 DDR_B_D41 DDR_B_D42 DDR_B_D43 DDR_B_D44 DDR_B_D45 DDR_B_D46 DDR_B_D47 DDR_B_D48 DDR_B_D49 DDR_B_D50 DDR_B_D51 DDR_B_D52 DDR_B_D53 DDR_B_D54 DDR_B_D55 DDR_B_D56 DDR_B_D57 DDR_B_D58 DDR_B_D59 DDR_B_D60 DDR_B_D61 DDR_B_D62 DDR_B_D63 AK47 AH46 AP47 AP46 AJ46 AJ48 AM48 AP48 AU47 AU46 BA48 AY48 AT47 AR47 BA47 BC47 BC46 BC44 BG43 BF43 BE45 BC41 BF40 BF41 BG38 BF38 BH35 BG35 BH40 BG39 BG34 BH34 BH14 BG12 BH11 BG8 BH12 BF11 BF8 BG7 BC5 BC6 AY3 AY1 BF6 BF5 BA1 BD3 AV2 AU3 AR3 AN2 AY2 AV1 AP3 AR1 AL1 AL2 AJ1 AH1 AM2 AM3 AH3 AJ3 SB_DQ_0 SB_DQ_1 SB_DQ_2 SB_DQ_3 SB_DQ_4 SB_DQ_5 SB_DQ_6 SB_DQ_7 SB_DQ_8 SB_DQ_9 SB_DQ_10 SB_DQ_11 SB_DQ_12 SB_DQ_13 SB_DQ_14 SB_DQ_15 SB_DQ_16 SB_DQ_17 SB_DQ_18 SB_DQ_19 SB_DQ_20 SB_DQ_21 SB_DQ_22 SB_DQ_23 SB_DQ_24 SB_DQ_25 SB_DQ_26 SB_DQ_27 SB_DQ_28 SB_DQ_29 SB_DQ_30 SB_DQ_31 SB_DQ_32 SB_DQ_33 SB_DQ_34 SB_DQ_35 SB_DQ_36 SB_DQ_37 SB_DQ_38 SB_DQ_39 SB_DQ_40 SB_DQ_41 SB_DQ_42 SB_DQ_43 SB_DQ_44 SB_DQ_45 SB_DQ_46 SB_DQ_47 SB_DQ_48 SB_DQ_49 SB_DQ_50 SB_DQ_51 SB_DQ_52 SB_DQ_53 SB_DQ_54 SB_DQ_55 SB_DQ_56 SB_DQ_57 SB_DQ_58 SB_DQ_59 SB_DQ_60 SB_DQ_61 SB_DQ_62 SB_DQ_63 SB_BS_0 SB_BS_1 SB_BS_2 SB_RAS# SB_CAS# SB_WE# BC16 BB17 BB33 AU17 BG16 BF14 DDR_B_BS0 DDR_B_BS1 DDR_B_BS2 DDR_B_RAS# DDR_B_CAS# DDR_B_WE# DDR_B_BS0 DDR_B_BS1 DDR_B_BS2 <15> <15> <15>
DDR_A_RAS# <14> DDR_A_CAS# <14> DDR_A_WE# <14>
DDR_B_RAS# <15> DDR_B_CAS# <15> DDR_B_WE# <15>
DDR_A_DM[0..7] SA_DM_0 SA_DM_1 SA_DM_2 SA_DM_3 SA_DM_4 SA_DM_5 SA_DM_6 SA_DM_7 AM37 AT41 AY41 AU39 BB12 AY6 AT7 AJ5 AJ44 AT44 BA43 BC37 AW12 BC8 AU8 AM7 AJ43 AT43 BA44 BD37 AY12 BD8 AU9 AM8 DDR_A_DM0 DDR_A_DM1 DDR_A_DM2 DDR_A_DM3 DDR_A_DM4 DDR_A_DM5 DDR_A_DM6 DDR_A_DM7 DDR_A_DQS0 DDR_A_DQS1 DDR_A_DQS2 DDR_A_DQS3 DDR_A_DQS4 DDR_A_DQS5 DDR_A_DQS6 DDR_A_DQS7 DDR_A_DQS#0 DDR_A_DQS#1 DDR_A_DQS#2 DDR_A_DQS#3 DDR_A_DQS#4 DDR_A_DQS#5 DDR_A_DQS#6 DDR_A_DQS#7 DDR_A_DQS[0..7]
<14>
A
<14>
SB_DM_0 SB_DM_1 SB_DM_2 SB_DM_3 SB_DM_4 SB_DM_5 SB_DM_6 SB_DM_7 SB_DQS_0 SB_DQS_1 SB_DQS_2 SB_DQS_3 SB_DQS_4 SB_DQS_5 SB_DQS_6 SB_DQS_7 SB_DQS#_0 SB_DQS#_1 SB_DQS#_2 SB_DQS#_3 SB_DQS#_4 SB_DQS#_5 SB_DQS#_6 SB_DQS#_7 SB_MA_0 SB_MA_1 SB_MA_2 SB_MA_3 SB_MA_4 SB_MA_5 SB_MA_6 SB_MA_7 SB_MA_8 SB_MA_9 SB_MA_10 SB_MA_11 SB_MA_12 SB_MA_13 SB_MA_14
AM47 AY47 BD40 BF35 BG11 BA3 AP1 AK2 AL47 AV48 BG41 BG37 BH9 BB2 AU1 AN6 AL46 AV47 BH41 BH37 BG9 BC2 AT2 AN5 AV17 BA25 BC25 AU25 AW25 BB28 AU28 AW28 AT33 BD33 BB16 AW33 AY33 BH15 AU33
DDR_B_DM0 DDR_B_DM1 DDR_B_DM2 DDR_B_DM3 DDR_B_DM4 DDR_B_DM5 DDR_B_DM6 DDR_B_DM7 DDR_B_DQS0 DDR_B_DQS1 DDR_B_DQS2 DDR_B_DQS3 DDR_B_DQS4 DDR_B_DQS5 DDR_B_DQS6 DDR_B_DQS7 DDR_B_DQS#0 DDR_B_DQS#1 DDR_B_DQS#2 DDR_B_DQS#3 DDR_B_DQS#4 DDR_B_DQS#5 DDR_B_DQS#6 DDR_B_DQS#7 DDR_B_MA0 DDR_B_MA1 DDR_B_MA2 DDR_B_MA3 DDR_B_MA4 DDR_B_MA5 DDR_B_MA6 DDR_B_MA7 DDR_B_MA8 DDR_B_MA9 DDR_B_MA10 DDR_B_MA11 DDR_B_MA12 DDR_B_MA13 DDR_B_MA14
DDR_B_DM[0..7]
<15>
B
C
MEMORY
SA_DQS_0 SA_DQS_1 SA_DQS_2 SA_DQS_3 SA_DQS_4 SA_DQS_5 SA_DQS_6 SA_DQS_7 SA_DQS#_0 SA_DQS#_1 SA_DQS#_2 SA_DQS#_3 SA_DQS#_4 SA_DQS#_5 SA_DQS#_6 SA_DQS#_7
DDR_B_DQS[0..7]
<15>
MEMORY
DDR_A_DQS#[0..7]
<14>
C
DDR_B_DQS#[0..7]
<15>
SYSTEM
DDR_A_MA[0..14] BA21 BC24 BG24 BH24 BG25 BA24 BD24 BG27 BF25 AW24 BC21 BG26 BH26 BH17 AY25 DDR_A_MA0 DDR_A_MA1 DDR_A_MA2 DDR_A_MA3 DDR_A_MA4 DDR_A_MA5 DDR_A_MA6 DDR_A_MA7 DDR_A_MA8 DDR_A_MA9 DDR_A_MA10 DDR_A_MA11 DDR_A_MA12 DDR_A_MA13 DDR_A_MA14
<14>
SYSTEM
DDR_B_MA[0..14]
<15>
SA_MA_0 SA_MA_1 SA_MA_2 SA_MA_3 SA_MA_4 SA_MA_5 SA_MA_6 SA_MA_7 SA_MA_8 SA_MA_9 SA_MA_10 SA_MA_11 SA_MA_12 SA_MA_13 SA_MA_14
DDR
CANTIGA ES_FCBGA1329 GM45@
DDR
GM45@
CANTIGA ES_FCBGA1329
B
B
A
A
Security Classification Issued Date 2008/11/24
Compal Secret Data
Deciphered Date 2009/12/31
Title
Compal Electronics, Inc. SCHEMATIC LA-4493
Document Number Rev D Sheet
1
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL Size AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D C DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
5 4 3 2
401689
Thursday, March 19, 2009 9 of 54
Date:

5
4
3
2
1
U2C <22> DPST_PWM 1 2 R1154 GM@ 0_0402_5% <22> GMCH_LCD_CLK <22> GMCH_LCD_DATA <22> GMCH_ENVDD R1155 LBKLT_EN LCTLA_CLK LCTLB_DATA GMCH_LCD_CLK GMCH_LCD_DATA
<18,36>
ENBKL
D
L32 G32 M32 M33 K33 J33 M29 C44 B43 E37 E38 C41 C40 B37 A37 H47 E46 G40 A40 H48 D45 F40 B40 A41 H38 G37 J37
L_BKLT_CTRL L_BKLT_EN L_CTRL_CLK L_CTRL_DATA L_DDC_CLK L_DDC_DATA L_VDD_EN LVDS_IBG LVDS_VBG LVDS_VREFH LVDS_VREFL LVDSA_CLK# LVDSA_CLK LVDSB_CLK# LVDSB_CLK LVDSA_DATA#_0 LVDSA_DATA#_1 LVDSA_DATA#_2 LVDSA_DATA#_3 LVDSA_DATA_0 LVDSA_DATA_1 LVDSA_DATA_2 LVDSA_DATA_3 LVDSB_DATA#_0 LVDSB_DATA#_1 LVDSB_DATA#_2 LVDSB_DATA#_3 LVDSB_DATA_0 LVDSB_DATA_1 LVDSB_DATA_2 LVDSB_DATA_3
PEG_COMPI PEG_COMPO PEG_RX#_0 PEG_RX#_1 PEG_RX#_2 PEG_RX#_3 PEG_RX#_4 PEG_RX#_5 PEG_RX#_6 PEG_RX#_7 PEG_RX#_8 PEG_RX#_9 PEG_RX#_10 PEG_RX#_11 PEG_RX#_12 PEG_RX#_13 PEG_RX#_14 PEG_RX#_15 PEG_RX_0 PEG_RX_1 PEG_RX_2 PEG_RX_3 PEG_RX_4 PEG_RX_5 PEG_RX_6 PEG_RX_7 PEG_RX_8 PEG_RX_9 PEG_RX_10 PEG_RX_11 PEG_RX_12 PEG_RX_13 PEG_RX_14 PEG_RX_15 PEG_TX#_0 PEG_TX#_1 PEG_TX#_2 PEG_TX#_3 PEG_TX#_4 PEG_TX#_5 PEG_TX#_6 PEG_TX#_7 PEG_TX#_8 PEG_TX#_9 PEG_TX#_10 PEG_TX#_11 PEG_TX#_12 PEG_TX#_13 PEG_TX#_14 PEG_TX#_15 PEG_TX_0 PEG_TX_1 PEG_TX_2 PEG_TX_3 PEG_TX_4 PEG_TX_5 PEG_TX_6 PEG_TX_7 PEG_TX_8 PEG_TX_9 PEG_TX_10 PEG_TX_11 PEG_TX_12 PEG_TX_13 PEG_TX_14 PEG_TX_15
GM45@
T37 T36 H44 J46 L44 L40 N41 P48 N44 T43 U43 Y43 Y48 Y36 AA43 AD37 AC47 AD39 H43 J44 L43 L41 N40 P47 N43 T42 U42 Y42 W47 Y37 AA42 AD36 AC48 AD40 J41 M46 M47 M40 M42 R48 N38 T40 U37 U40 Y40 AA46 AA37 AA40 AD43 AC46 J42 L46 M48 M39 M43 R47 N37 T39 U36 U39 Y39 Y46 AA36 AA39 AD42 AD46
PEG_COMP
10mils
R57
1
2
49.9_0402_1%
+1.05VS PCIE_MTX_C_GRX_N[0..15] PCIE_MTX_C_GRX_P[0..15] PCIE_GTX_C_MRX_N[0..15] PCIE_GTX_C_MRX_P[0..15] HDMI_PCIE_MTX_C_GRX_N[0..3] HDMI_PCIE_MTX_C_GRX_P[0..3] PCIE_MTX_C_GRX_N[0..15] <17> PCIE_MTX_C_GRX_P[0..15] <17> PCIE_GTX_C_MRX_N[0..15] <17> PCIE_GTX_C_MRX_P[0..15] <17> HDMI_PCIE_MTX_C_GRX_N[0..3] HDMI_PCIE_MTX_C_GRX_P[0..3] <30> <30>
D
1
GM@
2
LVDS_IBG 2.37K_0402_1% 2 1 R1153 GM@ 0_0402_5% GMCH_TXCLKGMCH_TXCLK+
<22> GMCH_TXCLK<22> GMCH_TXCLK+
<22> GMCH_TXOUT0<22> GMCH_TXOUT1<22> GMCH_TXOUT2<22> GMCH_TXOUT0+ <22> GMCH_TXOUT1+ <22> GMCH_TXOUT2+
GMCH_TXOUT0GMCH_TXOUT1GMCH_TXOUT2GMCH_TXOUT0+ GMCH_TXOUT1+ GMCH_TXOUT2+
PCIE_GTX_C_MRX_N0 PCIE_GTX_C_MRX_N1 PCIE_GTX_C_MRX_N2 PCIE_GTX_C_MRX_N3 PCIE_GTX_C_MRX_N4 PCIE_GTX_C_MRX_N5 PCIE_GTX_C_MRX_N6 PCIE_GTX_C_MRX_N7 PCIE_GTX_C_MRX_N8 PCIE_GTX_C_MRX_N9 PCIE_GTX_C_MRX_N10 PCIE_GTX_C_MRX_N11 PCIE_GTX_C_MRX_N12 PCIE_GTX_C_MRX_N13 PCIE_GTX_C_MRX_N14 PCIE_GTX_C_MRX_N15 PCIE_GTX_C_MRX_P0 PCIE_GTX_C_MRX_P1 PCIE_GTX_C_MRX_P2 PCIE_GTX_C_MRX_P3 PCIE_GTX_C_MRX_P4 PCIE_GTX_C_MRX_P5 PCIE_GTX_C_MRX_P6 PCIE_GTX_C_MRX_P7 PCIE_GTX_C_MRX_P8 PCIE_GTX_C_MRX_P9 PCIE_GTX_C_MRX_P10 PCIE_GTX_C_MRX_P11 PCIE_GTX_C_MRX_P12 PCIE_GTX_C_MRX_P13 PCIE_GTX_C_MRX_P14 PCIE_GTX_C_MRX_P15 PCIE_MTX_GRX_N0 PCIE_MTX_GRX_N1 PCIE_MTX_GRX_N2 PCIE_MTX_GRX_N3 PCIE_MTX_GRX_N4 PCIE_MTX_GRX_N5 PCIE_MTX_GRX_N6 PCIE_MTX_GRX_N7 PCIE_MTX_GRX_N8 PCIE_MTX_GRX_N9 PCIE_MTX_GRX_N10 PCIE_MTX_GRX_N11 PCIE_MTX_GRX_N12 PCIE_MTX_GRX_N13 PCIE_MTX_GRX_N14 PCIE_MTX_GRX_N15 PCIE_MTX_GRX_P0 PCIE_MTX_GRX_P1 PCIE_MTX_GRX_P2 PCIE_MTX_GRX_P3 PCIE_MTX_GRX_P4 PCIE_MTX_GRX_P5 PCIE_MTX_GRX_P6 PCIE_MTX_GRX_P7 PCIE_MTX_GRX_P8 PCIE_MTX_GRX_P9 PCIE_MTX_GRX_P10 PCIE_MTX_GRX_P11 PCIE_MTX_GRX_P12 PCIE_MTX_GRX_P13 PCIE_MTX_GRX_P14 PCIE_MTX_GRX_P15 C1290 1 C1292 1 C1294 1 C1296 1 C1298 1 C1300 1 C1302 1 C1304 1 C1306 1 C1308 1 C1310 1 C1312 1 C1314 1 C1316 1 C1318 1 C1320 1
C
PCI-EXPRESS
B42 G38 F37 K37
GRAPHICS
LVDS
CLOSE SPLIT POINT
PCIE_MTX_GRX_N0 1 2 HDMI_PCIE_MTX_C_GRX_N0 GM@ C1321 0.1U_0402_16V7K PCIE_MTX_GRX_N1 1 2 HDMI_PCIE_MTX_C_GRX_N1 GM@ C1322 0.1U_0402_16V7K PCIE_MTX_GRX_N2 1 2 HDMI_PCIE_MTX_C_GRX_N2 GM@ C1323 0.1U_0402_16V7K PCIE_MTX_GRX_N3 1 2 HDMI_PCIE_MTX_C_GRX_N3 GM@ C1324 0.1U_0402_16V7K PCIE_MTX_GRX_P0 1 2 HDMI_PCIE_MTX_C_GRX_P0 GM@ C1325 0.1U_0402_16V7K PCIE_MTX_GRX_P1 1 2 HDMI_PCIE_MTX_C_GRX_P1 GM@ C1326 0.1U_0402_16V7K PCIE_MTX_GRX_P2 1 2 HDMI_PCIE_MTX_C_GRX_P2 GM@ C1327 0.1U_0402_16V7K PCIE_MTX_GRX_P3 1 2 HDMI_PCIE_MTX_C_GRX_P3 GM@ C1328 0.1U_0402_16V7K PCIE_GTX_C_MRX_P3 2 1 TMDS_B_HPD# <30> R1171 GM@ 0_0402_5% C1289 1 2 PM@ 0.1U_0402_16V7K C1291 1 2 PM@ 0.1U_0402_16V7K C1293 1 0.1U_0402_16V7K 2 PM@ C1295 1 2 PM@ 0.1U_0402_16V7K C1297 1 2 PM@ 0.1U_0402_16V7K C1299 1 2 PM@ 0.1U_0402_16V7K C1301 1 2 PM@ 0.1U_0402_16V7K C1303 1 2 PM@ 0.1U_0402_16V7K C1305 1 2 PM@ 0.1U_0402_16V7K C1307 1 PM@ 0.1U_0402_16V7K 2 C1309 1 2 PM@ 0.1U_0402_16V7K C1311 1 PM@ 0.1U_0402_16V7K 2 C1313 1 2 PM@ 0.1U_0402_16V7K C1315 1 2 PM@ 0.1U_0402_16V7K C1317 1 2 PM@ 0.1U_0402_16V7K C1319 1 2 PM@ 0.1U_0402_16V7K
C
Change to 0Ohm when use PM chip
GMCH_TV_COMPS GMCH_TV_LUMA GMCH_TV_CRMA
F25 H25 K25 H24
TVA_DAC TVB_DAC TVC_DAC
R107 75_0402_1% GM@
R108 R93 75_0402_1% 75_0402_1% GM@ GM@ TV_DCONSEL_0 TV_DCONSEL_1
TV_RTN
C31 E32
TV_DCONSEL_0 TV_DCONSEL_1
2 PM@ 0.1U_0402_16V7K PCIE_MTX_C_GRX_N0 PCIE_MTX_C_GRX_N1 2 PM@ 0.1U_0402_16V7K PCIE_MTX_C_GRX_N2 PCIE_MTX_C_GRX_N3 PM@ 0.1U_0402_16V7K PCIE_MTX_C_GRX_N4 2 PCIE_MTX_C_GRX_N5 2 PM@ 0.1U_0402_16V7K PCIE_MTX_C_GRX_N6 PCIE_MTX_C_GRX_N7 PM@ 0.1U_0402_16V7K PCIE_MTX_C_GRX_N8 2 PCIE_MTX_C_GRX_N9 2 PM@ 0.1U_0402_16V7K PCIE_MTX_C_GRX_N10 PCIE_MTX_C_GRX_N11 PM@ 0.1U_0402_16V7K PCIE_MTX_C_GRX_N12 2 PCIE_MTX_C_GRX_N13 2 PM@ 0.1U_0402_16V7K PCIE_MTX_C_GRX_N14 PCIE_MTX_C_GRX_N15 2 PM@ 0.1U_0402_16V7K PCIE_MTX_C_GRX_P0 PCIE_MTX_C_GRX_P1 2 PM@ 0.1U_0402_16V7K PCIE_MTX_C_GRX_P2 PCIE_MTX_C_GRX_P3 2 PM@ 0.1U_0402_16V7K PCIE_MTX_C_GRX_P4 PCIE_MTX_C_GRX_P5 2 PM@ 0.1U_0402_16V7K PCIE_MTX_C_GRX_P6 PCIE_MTX_C_GRX_P7 2 PM@ 0.1U_0402_16V7K PCIE_MTX_C_GRX_P8 PCIE_MTX_C_GRX_P9 2 PM@ 0.1U_0402_16V7K PCIE_MTX_C_GRX_P10 PCIE_MTX_C_GRX_P11 2 PM@ 0.1U_0402_16V7K PCIE_MTX_C_GRX_P12 PCIE_MTX_C_GRX_P13 PM@ 0.1U_0402_16V7K PCIE_MTX_C_GRX_P14 2 PCIE_MTX_C_GRX_P15
2
2
2
TV
1
1
1
Change to 0Ohm when use PM chip
<23> GMCH_CRT_B <23> GMCH_CRT_G <23> GMCH_CRT_R
B
2 GM@ R1159 2 GM@ R1160 2 GM@ R1161
E28 G28 J28 G29
GMCH_CRT_CLK GMCH_CRT_DATA CRT_IREF
1 1 1
CRT_BLUE CRT_GREEN
150_0402_1% 150_0402_1% 150_0402_1%
VGA
CRT_RED CRT_IRTN CRT_DDC_CLK CRT_DDC_DATA CRT_HSYNC CRT_TVO_IREF CRT_VSYNC
B
<23> GMCH_CRT_CLK <23> GMCH_CRT_DATA <23> GMCH_CRT_HSYNC
2 R1162 PM@
1
0_0402_5%
H32 J32 J29 E29 L29
<23> GMCH_CRT_VSYNC +3VS
2
2 R1163 PM@
1
0_0402_5%
R1164 1 GM@ R1166 1 GM@ R1167 1 GM@ R1168 1 GM@ R1169 1 GM@ R1170 1 GM@
2 2.2K_0402_5% 2 2.2K_0402_5% 2 10K_0402_5% 2 10K_0402_5% 2 2.2K_0402_5% 2 2.2K_0402_5%
GMCH_LCD_CLK
R1165 1.02K_0402_1% GM@
CANTIGA ES_FCBGA1329
LCTLB_DATA LCTLA_CLK GMCH_CRT_CLK GMCH_CRT_DATA
A
1
GMCH_LCD_DATA
A
R1173 1
2 100K_0402_5%
LBKLT_EN
Security Classification Issued Date 2008/11/24
Compal Secret Data
Deciphered Date 2009/12/31
Title
Compal Electronics, Inc. SCHEMATIC LA-4493
Rev D Sheet
1
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL Size Document Number AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Custom DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
401689
Date:
Thursday, March 19, 2009
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