FPGA可编程逻辑器件芯片EP1S25F672C-7N中文规格书
Table 4–20 provides information on recommended input clock jitter for each mode.
Notes to Table 4–19:(1)Dedicated REFCLK pins were used to drive the input reference clocks.(2)Jitter numbers specified are valid for the stated conditions only.
(3)Refer to the protocol characterization documents for detailed information.
(4)HiGig configuration is available in a -3 speed grade only. For more information, refer to the Stratix II GX Transceiver Architecture Overview chapter in volume 2 of the Stratix II GX Device Handbook .
(5)Stratix II GX transceivers meet CEI jitter generation specification of 0.3 UI for a V OD range of 400mV to 1000 mV . (6)The Sinusoidal Jitter Tolerance Mask is defined only for low voltage (LV) variant of CPRI.(7)The jitter numbers for SONET/SDH are compliant to the GR-253-CORE Issue 3 Specification.(8)The jitter numbers for Fibre Channel are compliant to the FC-PI-4 Specification revision 6.10.(9)The jitter numbers for XAUI are compliant to the IEEE802.3ae-2002 Specification.(10)The jitter numbers for PCI Express are compliant to the PCIe Base Specification 2.0.(11)The jitter numbers for Serial RapidIO are compliant to the RapidIO Specification 1.3.(12)The jitter numbers for GIGE are compliant to the IEEE802.3-2002 Specification.(13)The jitter numbers for HiGig are compliant to the IEEE802.3ae-2002 Specification.(14)The jitter numbers for (OIF) CEI are compliant to the OIF-CEI-02.0 Specification.(15)The jitter numbers for CPRI are compliant to the CPRI Specification V2.1.
(16)The HD-SDI and 3G-SDI jitter numbers are compliant to the SMPTE292M and SMPTE424M Specifications.
(17)The Fibre Channel transmitter jitter generation numbers are compliant to the specification at βT interoperability point.(18)
The Fibre Channel receiver jitter tolerance numbers are compliant to the specification at βR interoperability point.
Table 4–19.Stratix II GX Transceiver Block AC Specification Notes (1), (2), (3)(Part 19 of 19)
Symbol/Description
Conditions
-3 Speed
Commercial Speed
Grade -4 Speed Commercial and Industrial Speed
Grade -5 Speed
Commercial Speed
Grade Unit
Min
Typ Max
Min
Typ
Max
Min
Typ
Max
Table 4–20.Recommended Input Clock Jitter (Part 1 of 2)Mode
Reference Clock (MHz)
Vectron LVPECL XO Type/Model
Frequency
Range (MHz)
RMS Jitter (12 kHz to 20 MHz) (ps)Period Jitter
(Peak to
Peak) (ps)
Phase Noise
at 1 MHz (dB c/Hz)
PCI-E 100VCC6-Q/R 10 to 2700.323-149.9957(OIF) CEI PHY 156.25VCC6-Q/R 10 to 2700.323-146.2169622.08VCC6-Q 270 to 800230Not available GIGE 62.5VCC6-Q/R 10 to 2700.323-149.9957125VCC6-Q/R 10 to 2700.323-146.9957XAUI
156.25
VCC6-Q/R
10 to 270
0.3
23
-146.2169
Table4–29. 2.5-V LVDS I/O Specifications
Symbol Parameter Conditions Minimum Typical Maximum Unit
2.375 2.5 2.625V V CCIO I/O supply voltage for left and
right I/O banks (1, 2, 5, and
6)
V ID Input differential voltage
100350900mV swing (single-ended)
V ICM Input common mode voltage2001,2501,800mV
R L = 100 Ω250450mV V OD Output differential voltage
(single-ended)
R L = 100 Ω 1.125 1.375V V OCM Output common mode
voltage
90100110ΩR L Receiver differential input
discrete resistor (external to
Stratix II GX devices)
Table4–30.3.3-V LVDS I/O Specifications
Symbol Parameter Conditions Minimum Typical Maximum Unit V CCIO (1)I/O supply voltage for top and
3.135 3.3 3.465V
bottom PLL banks (9, 10, 11,
and 12)
100350900mV V ID Input differential voltage
swing (single-ended)
V ICM Input common mode voltage2001,2501,800mV V OD Output differential voltage
R L = 100 Ω250710mV (single-ended)
R L = 100 Ω8401,570mV V OCM Output common mode
voltage
90100110ΩR L Receiver differential input
discrete resistor (external to
Stratix II GX devices)
Note to Table4–30:
(1)The top and bottom clock input differential buffers in I/O banks 3, 4, 7, and 8 are powered by V CCINT, not V CCIO.
The PLL clock output/feedback differential buffers are powered by VCC_PLL_OUT. For differential clock
output/feedback operation, connect VCC_PLL_OUT to 3.3 V.
Operating Conditions
Table4–31.PCML Specifications Note(1)
Symbol Parameter References Reference Clock
3.3-V PCML 1.5-V PCML 1.2-V PCML Reference clock supported PCML standards
V ID Peak-to-peak differential input
voltage The specifications are located in the Reference Clock section of T able4–6 on page4–4.
The specifications listed in T able4–6 are applicable to PCML input standards.
V ICM Input common mode voltage R On-chip termination resistors Receiver
3.3-V PCML 1.5-V PCML 1.2-V PCML Receiver supported PCML standards
V ID Peak-to-peak differential input
voltage The specifications are located in the Receiver section of
T able4–6 on page4–4.
The specifications listed in T able4–6 are applicable to PCML input standards.
V ICM Input common mode voltage R On-chip termination resistors Transmitter
1.5-V PCML 1.2-V PCML Transmitter supported PCML standards
V CCH Output buffer supply voltage The specifications are located in Table4–5 on page4–4.
V OD Peak-to-peak differential output
voltage The specifications are located in Tables4–7, 4–8, 4–9, 4–10, 4–11, and 4–12.
The specifications listed in these tables are applicable to PCML output standards.
V OCM Output common mode voltage The specifications are located in the Transmitter section of
T able4–6 on page4–4.
The specifications listed in T able4–6 are applicable to PCML
output standards.
R On-chip termination resistors
Note to Table4–31:
(1)Stratix II GX devices support PCML input and output on GXB banks 13, 14, 15, 16, and 17. This table references
Stratix II GX PCML specifications that are located in other sections of the Stratix II GX Device Handbook.
DC and Switching Characteristics
Power Consumption Altera offers two ways to calculate power for a design: the Excel-based PowerPlay early power estimator power calculator and the Quartus? II PowerPlay power analyzer feature.
The interactive Excel-based PowerPlay early power estimator is typically used prior to designing the FPGA in order to get an estimate of device power. The Quartus II PowerPlay power analyzer provides better quality estimates based on the specifics of the design after place-and-route is complete. The power analyzer can apply a combination of user-entered, simulation-derived and estimated signal activities which, combined with detailed circuit models, can yield very accurate power estimates.
In both cases, these calculations should only be used as an estimation of power, not as a specification.
f For more information on PowerPlay tools, refer to the PowerPlay Early
Power Estimators (EPE) and Power Analyzer, the Quartus II PowerPlay
Analysis and Optimization Technology, and the PowerPlay Power Analyzer
chapter in volume 3 of the Quartus II Handbook. The PowerPlay early
power estimators are available on the Altera web site at
www.altera. com.
1See Table4–23 on page42 for typical I CC standby specifications. Timing Model The DirectDrive technology and MultiTrack interconnect ensure
predictable performance, accurate simulation, and accurate timing
analysis across all Stratix II GX device densities and speed grades. This
section describes and specifies the performance, internal, external, and
PLL timing specifications.
All specifications are representative of worst-case supply voltage and
junction temperature conditions.
Preliminary and Final Timing
Timing models can have either preliminary or final status. The Quartus II
software issues an informational message during the design compilation
if the timing models are preliminary. Table4–52 shows the status of the
Stratix II GX device timing models.
Preliminary status means the timing model is subject to change. Initially,
timing numbers are created using simulation results, process data, and
other known parameters. These tests are used to make the preliminary
numbers as close to the actual timing parameters as possible.