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HMP8156中文资料

August 1997HMP8156

NTSC/PAL Encoder

Features

?(M) NTSC and (B, D, G, H, I, M, N, CN) PAL Operation ?ITU-R BT.601 and Square Pixel Operation

?Digital Input Formats

-4:2:2 YCbCr

-8-Bit or 16-Bit

-4:4:4 RGB

-16-Bit (5, 6, 5) or 24-Bit (8, 8, 8)

-Linear or Gamma-Corrected

-8-Bit Parallel ITU-R BT.656

-Seven Overlay Colors

?Analog Output Formats

-Y/C + Two Composite

-RGB + Composite (SCART)

?Flexible Video Timing Control

-Timing Master or Slave

-Selectable Polarity on Each Control Signal

-Programmable Blank Output Timing

-Field Output

?Closed Caption Encoding for NTSC and PAL

?2x Upscaling of SIF Video

?Four 2x Oversampling, 10-Bit DACs

?I2C Interface

?Verilog Models Available. . . . . . . . . . . . . . . . . . . . . . . . . Applications

?Multimedia PCs

?Video Conferencing

?Video Editing

?Related Products

-NTSC/PAL Encoders: HMP8154

-NTSC/PAL Decoders: HMP8112A, HMP8115Description

The HMP8156 NTSC and PAL encoder is designed for use in systems requiring the generation of high-quality NTSC and P AL video from digital image data.

YCbCr or RGB digital video data drive the P0-P23 inputs. Overlay inputs are processed and the data is 2x upsampled. The Y data is optionally lowpass ?ltered to 5MHz and drives the Y analog output. Cb and Cr are each lowpass ?ltered to 1.3MHz, quadrature modulated, and summed. The result drives the C analog output. The digital Y and C data are also added together and drive the two composite analog outputs. The YCbCr data may also be converted to RGB data to drive the DACs, allowing support for the European SCART con-nector.

The DACs can drive doubly-terminated (37.5?) lines, and run at a 2x oversampling rate to simplify the analog output ?lter requirements.

Table of Contents Page Functional Block Diagram. . . . . . . . . . . . . . . . . . . . . . . . .2 Functional Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . .3 Pixel Data Input Formats . . . . . . . . . . . . . . . . . . . . . . . . .3 Input Processing. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .4 Pixel Input and Control Signal Timing. . . . . . . . . . . . . . . .5 Video Timing Control . . . . . . . . . . . . . . . . . . . . . . . . . . . .10 Video Processing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .12 Analog Outputs. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .14 Host Interfaces . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .15 Pinout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .22 Pin Descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .22 Applications Information. . . . . . . . . . . . . . . . . . . . . . . . . .30 Evaluation Kits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .32

Ordering Information

PART NUMBER

TEMP.

RANGE (o C)PACKAGE PKG. NO.

HMP8156CN0 to 7064 PQFP Q64.14x14

HMP8156EVAL1Daughter Card Evaluation Platform (Note)

HMP8156EVAL2Frame Grabber Evaluation Platform (Note)

NOTE:Described in the Applications Section

File Number4269.3 CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.

HMP8156

F u n c t i o n a l B l o c k D i a g r a m

O V E R L A Y P R O C E S S I N G

S A

S C L

S D A

R E S E T

H O S T I N T E R F A C E

O P T I O N A L G A M M A C O R R E C T I O N

P 0 - P 23

4:2:2 T O 4:4:4 S A M P L E C O N V E R S I O N

C O L O R S P A C E C O N V E R S I O N

4:4:4Y /C b /C r (O P T I O N A L )

L P F I L T E R Y C b /C r C L O S E D C A P T I O N I N G P R O C E S S I N G

D A C D A C

D A C

D A C Y /G

N T S C /N T S C /C /B

P A L 1

P A L 2/R

H S Y N C

V S Y N C

B L A N K

C L K

V I D E O T I M I N G C L K 2

F I E L D

C O N T R O L

V R E F

F S A D J U S T

I N T E R N A L 1.225V R E F E R E N C E

2 X U P S A M P L E C H R O M A M O D U L A T I O N

L P F I L T E R

4:4:4T O 8:8:8

(2:2:2 S I F )

O P T I O N A L 2X U P S C A L I N G (S I F M O D E )

Functional Operation

The HMP8156 is a fully integrated digital encoder. It accepts digital video input data and generates four analog video out-put signals. The input data format is selectable and includes YCbCr, RGB, and overlay data. The outputs are con?gurable to be either two composite video signals and Y/C (S-Video) or one composite and component RGB video.

The HMP8156 accepts pixel data in one of several formats and transforms it into 4:4:4 sampled luminance and chromi-nance (YCbCr) data. If enabled, the encoder also mixes overlay data with the input data. The encoder then interpo-lates the YCbCr data to twice the pixel rate and low pass ?l-ters it to match the bandwidth of the video output format. If enabled, the encoder also adds Closed Captioning informa-tion to the Y data. At the same time, the encoder modulates the chrominance data with a digitally synthesized subcarrier. Finally, the encoder outputs the luminance, chrominance, and their sum as analog signals using 10-bit D/A converters. The HMP8156 provides operating modes to support all ver-sions of the NTSC and P AL standards and accepts full and SIF size input data with rectangular (ITU-R BT.601) and square pixel ratios. It operates from a single clock at twice the pixel clock rate determined by the operating mode.

The HMP8156’s video timing control is ?exible. It may oper-ate as the master generating the system’s video timing con-trol signals or it may accept external timing controls. The polarity of the timing controls and the number of active pixels and lines are programmable.Pixel Data Input Formats

The HMP8156 accepts pixel data via the P0-P23 input pins. The de?nition of each pixel input pin is determined by the input format selected in the input format register. The de?ni-tion for each mode is shown in T able 1.

YCbCr Pixel Data

The HMP8156 accepts 4:2:2 sampled YCbCr input data. The luminance and color difference signals are each 8 bits, scaled 0 to 255. Values outside their nominal ranges (16-235 for Y and 16-240 for Cb and Cr) are processed normally. The color difference signals are time multiplexed into one 8-bit bus beginning with a Cb sample. The Y and CbCr busses may be input in parallel (16-bit mode) or may be time multi-plexed and input as a single bus (8-bit mode). The single bus may also contain SAV and EAV video timing reference codes (ITU-R BT.656 mode).

RGB Data

The HMP8156 accepts 4:4:4 sampled RGB component video input data. The color signals may be (8,8,8) for 24-bit mode or (5,6,5) for 16-bit mode. In 24-bit mode, they are scaled 0 to 255, black to white. In 16-bit mode, the encoder left shifts the input so that it has the same scale as 24-bit input. The RGB data may be linear or gamma corrected; if enabled, the encoder will gamma correct the input data. Overlay Data

The HMP8156 accepts 5 bits of pixel overlay input data and combines it with the input pixel data. The data speci?es an overlay color and the fractions of the new and original colors to be summed.

Blue Screen Generation

In blue screen mode, the HMP8156 ignores the pixel input data and generates a solid, blue screen. The overlay inputs may be used to place information over the blue screen.

Input Processing

COLOR SPACE CONVERSION

For linear RGB input formats, the encoder applies gamma-correction using a selectable gamma value of 1/2.2 or 1/2.8. The gamma-corrected RGB data from either the correction function in linear mode or the input port otherwise is con-verted to 4:4:4 sampled YCbCr data.

For the YCbCr input formats, the encoder converts the 4:2:2 sampled data to 4:4:4 sampled data. The conversion is done

by 2x upsampling the Cb and Cr data. The upsampling func-tion uses linear interpolation.

OVERLAY PROCESSING

The HMP8156 accepts overlay data via the OL0-OL2, M0, and M1 pins. Overlay mixing is done using the 4:4:4 YCbCr pixel data from the color space converter. The YCbCr data following overlay processing is used as input data by the video processing functions.

The OL0-OL2 inputs select the color to be mixed with the pixel data. Overlay colors 1-7 are standard color bar colors. Overlay color 0 is special and disables mixing on a pixel by pixel basis. The overlay color palette is shown in Table 2.Note that overlay capability is not available when the 24-bit RGB input format is used.

The encoder provides 4 methods for mixing the overlay data with the pixel data: disabled, external mixing, internal mixing and no mixing. The method used is selected in the input for-mat control register.

Overlay Mixing: Disabled

When overlay mixing is disabled, the OL0-OL2, M0, and M1 inputs are ignored and the pixel data is not changed. Overlay Mixing: External

When external overlay mixing is selected, mixing of overlay data and pixel data is controlled by the M1 and M0 inputs. M1 and M0 indicate the mixing level between the pixel inputs and the overlay inputs, on a pixel-by-pixel basis. M1 and M0 are ignored if OL2-OL0 = 000. Otherwise, they select the percentage of each color to sum as shown in T able 3.

TABLE 1.PIXEL DATA INPUT FORMATS

PIN NAME 16-BIT

4:2:2

YCBCR

8-BIT

4:2:2

YCBCR BT.656

BLUE

SCREEN

16-BIT

RGB

(5, 6, 5)

24-BIT

RGB

P0 P1 P2 P3 P4 P5 P6 P7Cb0, Cr0

Cb1, Cr1

Cb2, Cr2

Cb3, Cr3

Cb4, Cr4

Cb5, Cr5

Cb6, Cr6

Cb7, Cr7

Ignored B0

P8 P9 P10 P11 P12 P13 P14 P15Y0

Y0, Cb0, Cr0

Y1, Cb1, Cr1

Y2, Cb2, Cr2

Y3, Cb3, Cr3

Y4, Cb4, Cr4

Y5, Cb5, Cr5

Y6, Cb6, Cr6

Y7, Cb7, Cr7

YCbCr Data,

SAV and EAV

Sequences

Ignored G3

P16 P17 P18 P19 P20 P21 P22 P23OL0

OL1

OL2

TABLE 2.OVERLAY COLOR PALETTE

OL2-OL0COLOR

000

001

010

011

100

101

110

111

Pixel Data

75% Blue

75% Red

75% Magenta

75% Green

75% Cyan

75% Yellow

100% White

In external mixing mode, there is no minimum number of pix-els an overlay color or pixel color must be selected. The mix-ing level may also vary at any rate.

Overlay Mixing: Internal

Mixing of overlay and pixel data may also be controlled inter-nally, and the M1 and M0 input pins are ignored. A transition from pixel data to overlays, from overlays to pixel data, or between different overlay colors triggers the mixing function. An overlay color must be selected for a minimum of three pixels for proper overlay operation in this mode. Internal overlay mixing should not be used with the BT.656 input for-mat.

When going from pixel to overlay data, mixing starts one pixel before the selection of the overlay color (OL2-OL1!= 000). The ?rst pixel output before the overlay uses 12.5% overlay color plus 87.5% pixel color. The next output is aligned with the selection of the overlay color and uses 87.5% overlay color plus 12.5% pixel color. Additional outputs use 100% overlay color.

When going from overlay to pixel data, mixing starts one pixel before the selection of the pixel color (OL2-OL0 = 000). The last pixel output of the overlay uses 87.5% overlay color plus 12.5% pixel color. The next output uses 12.5% overlay color plus 87.5% pixel color. Additional outputs use 100% pixel color.

When going from one overlay color to another, mixing starts one pixel before the selection of the new overlay color, and uses 12.5% new overlay color plus 87.5% old overlay color. The next output is aligned with the selection of the new over-lay color and uses 87.5% new overlay color plus 12.5% old overlay color. Additional outputs use 100% new overlay color.

Overlay Mixing: No Mixing

With no overlay mixing selected, whenever the OL0-OL2 inputs are non-zero, the overlay color is displayed. The M0 and M1 inputs are ignored, and no internal mixing is done. Essentially, this is a hard switch between overlay and pixel data. In this mode, there is no minimum number of pixels an overlay color or pixel color must be selected.

2X Upscaling

Following overlay processing, 2X upscaling may optionally be applied to the pixel data. In this mode, the HMP8156 accepts SIF resolution video at 50 or 59.94frames per sec-ond and generates standard interlaced video at 262.5 lines per ?eld (240 active) at 59.94?elds per second for (M, NSM) NTSC and (M) PAL, and 312.5 lines per ?eld (288 active) at 50 ?elds per second for (B, D, G, H, I, N, CN) PAL.This mode of operation allows SIF video to be upscaled to full resolution and recorded on a VCR or displayed on a TV. The input pixel data rate is reduced by half when 2X upscal-ing is enabled. The color space conversion generates, and the overlay mixer uses, 2:2:2 YCbCr data instead of 4:4:4 data. For rectangular pixel NTSC and P AL video, the input rate is 6.75MHz during the active portion of each line instead of 13.5MHz. Example SIF input resolutions and resulting output resolutions are shown in T able 4.

The HMP8156 performs horizontal 2X upscaling by linear interpolation. The vertical scaling is done by line duplication. For typical line duplication, the same frame of SIF pixel input data is used for both the odd and even ?elds. Note that a frame of SIF size input has about the same number of lines as a ?eld of full size input. After 2X upscaling, the input is 4:4:4 YCbCr data ready for video processing.

Pixel Input and Control Signal Timing

The pixel input timing and the video control signal input/out-put timing of the HMP8156 depend on the part’s operating mode. The periods when the encoder samples its inputs and generates its outputs are summarized in Table 5.

Figures 1-9 show the timing of CLK, CLK2,BLANK, and the pixel and overlay input data with respect to each other. BLANK may be an input or an output; the ?gures show both. When it is an input,BLANK must arrive coincident with the pixel and overlay input data; all are sampled at the same time.

When BLANK is an output, its timing with respect to the pixel and overlay inputs depends on the blank timing select bit in the timing_I/O_1 register. If the bit is cleared, the HMP8156 deasserts BLANK one CLK cycle before it samples the pixel and overlay inputs. As shown in the timing ?gures, the encoder samples the inputs 1-7 CLK2 periods after negating BLANK, depending on the operating mode.

If the bit is set, the encoder deasserts BLANK during the same CLK cycle in which it samples the input data. In effect, the input data must arrive one CLK cycle earlier than when the bit is cleared. This mode is not shown in the ?gures.

TABLE 3.OVERLAY MIXING FACTORS

M1, M0% OVERLAY

COLOR

% PIXEL

COLOR

00 01 10 11

12.5

87.5

100

87.5

12.5

TABLE 4.TYPICAL RESOLUTIONS FOR 2X UPSCALING

INPUT ACTIVE

RESOLUTION

OUTPUT ACTIVE

RESOLUTION

352 x 240

352 x 288

320 x 240

384 x 288

704 x 480

704 x 576

640 x 480

768 x 576

8-Bit YCbCr Format without 2X Upscaling

When 8-bit YCbCr format is selected and 2X upscaling is not enabled, the data is latched on each rising edge of CLK2.The pixel data must be [Cb Y Cr Y’ Cb Y Cr Y’...], with the ?rst active data each scan line being Cb data. Overlay data is latched when the Y input data is latched. The pixel and overlay input timing is shown in Figure 1.

As inputs,BLANK,HSYNC, and VSYNC are latched on each rising edge of CLK2. As outputs,BLANK,HSYNC, and VSYNC are output following the rising edge of CLK2. If the CLK pin is con?gured as an input, it is ignored. If con?gured as an output, it is one-half the CLK2 frequency

8-Bit YCbCr Format with 2X Upscaling

When 8-bit YCbCr format is selected, the data is latched on the rising edge of CLK2 while CLK is low. The pixel data must be [Cb Y Cr Y’ Cb Y Cr Y’...], with the ?rst active data each scan line being Cb data. Overlay data is latched on the rising edge of CLK2 that latches Y pixel input data. The pixel and overlay input timing is shown in Figure 2.

As inputs,BLANK,HSYNC, and VSYNC are latched on the rising edge of CLK2 while CLK is low. As outputs,HSYNC,VSYNC, and BLANK are output following the rising edge of CLK2 while CLK is high. In this mode of operation, CLK is one-half the CLK2 frequency.

TABLE 5.PIXEL INPUT AND CONTROL SIGNAL I/O TIMING

INPUT FORMAT 2X U P S C A L I N G

INPUT PORT SAMPLING

VIDEO TIMING CONTROL (NOTE)

CLK FREQUENCY

PIXEL DATA OVERLAY DATA INPUT SAMPLE OUTPUT ON INPUT OUTPUT 8-Bit YCbCr

Off

Every rising edge of CLK2Same edge that latches Y Every rising edge of CLK2Any rising edge of CLK2

Ignored

One-half CLK2

On Rising edge of CLK2 when CLK is low.

Same edge that latches Y data

Rising edge of CLK2 when CLK is low.

Rising edge of CLK2 when CLK is high.

One-half CLK2

16-Bit YCbCr,16-Bit RGB,

24-Bit RGB

Off Rising edge of CLK2 when CLK is low Rising edge of CLK2 when CLK is high.

One-half CLK2

On 2nd rising edge of CLK2 when CLK is low Either rising

CLK2 edge when CLK is high One-fourth CLK2

BT.656Off

Every rising edge of CLK2Same edge that latches Y

Not Allowed Any rising edge of CLK2

Ignored

One-half CLK2

On Not Available

NOTE:Video timing control signals include HSYNC,VSYNC,BLANK and FIELD. The sync and blanking I/O directions are independent;

FIELD is always an output.

FIGURE 1.PIXEL AND OVERLAY INPUT TIMING - 8-BIT YCBCR WITHOUT 2X UPSCALING

Cb 0Y 0Cr 0Y 1Cb 2Y 2CLK2

P8-P15BLANK (INPUT)PIXEL 0PIXEL 1PIXEL 2OL0-OL2,M1, M0Y N

PIXEL N

BLANK (OUTPUT)

16-Bit YCbCr, 16-Bit RGB, 24-Bit RGB Formats without 2X Upscaling

When 16-bit YCbCr, 16-bit RGB data, or 24-bit RGB format is selected without 2X upscaling, the pixel data is latched on the rising edge of CLK2 while CLK is low. Overlay data is also latched on the rising edge of CLK2 while CLK is low.The pixel and overlay input timing is shown in Figures 3 - 5.As inputs,BLANK,HSYNC, and VSYNC are latched on the rising edge of CLK2 while CLK is low. As outputs,HSYNC,VSYNC, and BLANK are output following the rising edge of CLK2 while CLK is high. In these modes of operation, CLK is one-half the CLK2 frequency.

16-Bit YCbCr, 16-Bit RGB, 24-Bit RGB Formats with 2X Upscaling

When 16-bit YCbCr, 16-bit RGB data, or 24-bit RGB format is selected and 2X upscaling is enabled, data is latched on the rising edge of CLK2 while CLK is low. Overlay data is latched on the rising edge of CLK2 while CLK is low. The pixel and overlay input timing is shown in Figures 6-8As inputs,BLANK,HSYNC, and VSYNC are latched on the rising edge of CLK2 while CLK is low. As outputs,HSYNC,VSYNC, and BLANK are output following the rising edge of CLK2 while CLK is high. CLK is one-fourth the CLK2 fre-quency.

FIGURE 2.PIXEL AND OVERLAY INPUT TIMING - 8-BIT YCBCR WITH 2X UPSCALING

CLK

Cb 0

Y 0

Cr 0

Y 1

Cb 2

Y 2

P8-P15BLANK (INPUT)PIXEL 0

PIXEL 1

PIXEL 2

OL0-OL2,M1, M0Y N

PIXEL N

BLANK (OUTPUT)

FIGURE 3.PIXEL AND OVERLAY INPUT TIMING 6-BIT YCBCR WITHOUT 2X UPSCALING

0Y 1Y

2Y 3Y

4Y 5CLK

P8-P15BLANK (INPUT)Cb 0Cr 0Cb 2Cr 2Cb 4Cr 4P0-P7PIXEL 0PIXEL 1PIXEL 2PIXEL 3PIXEL 4PIXEL 5OL0-OL2,M1, M0CLK2

Y N

Cr N-1

PIXEL N

BLANK (OUTPUT)

FIGURE 4.PIXEL AND OVERLAY INPUT TIMING - 16-BIT RGB WITHOUT 2X UPSCALING

FIGURE 5.PIXEL AND OVERLAY INPUT TIMING - 24-BIT RGB WITHOUT 2X UPSCALING

FIGURE 6.PIXEL AND OVERLAY INPUT TIMING - 16-BIT YCBCR WITH 2X UPSAMPLING

RGB 0RGB 1RGB 2RGB 3RGB 4RGB 5CLK

P0-P15

BLANK (INPUT)PIXEL 0PIXEL 1PIXEL 2PIXEL 3PIXEL 4PIXEL 5OL0-OL2,M1, M0RGB N

PIXEL N

BLANK (OUTPUT)

RGB 0RGB 1RGB 2RGB 3RGB 4RGB 5CLK

P0-P24

BLANK (INPUT)CLK2

RGB N

BLANK (OUTPUT)

BLANK (INPUT)P8-P15

CLK2

Y 0Y 1Y N

CLK

BLANK (OUTPUT)

OL0-OL2,M1, M0PIXEL 0PIXEL 1PIXEL N

P0-P7

Cb 0Cr 0Cr N-1

8-Bit Parallel ITU-R BT.656 Format

When ITU-R BT .656 format is selected, data is latched on each rising edge of CLK2. Overlay data is latched when the Y input data is latched. However, the overlay data must arrive three pixels after its corresponding Y data. The pixel and overlay input timing is shown in Figure 9.

As inputs, the BLANK,HSYNC, and VSYNC pins are ignored since all timing is derived from the EAV and SAV sequences within the data stream. As outputs,BLANK,

HSYNC and VSYNC are output following the rising edge of CLK2. If the CLK pin is con?gured as an input, it is ignored. If con?gured as an output, it is one-half the CLK2 frequency.Square pixel operation, overlay processing with internal mix-ing, and SIF mode 2X upsampling are not supported for the BT.656 input format. Also, the HSYNC,VSYNC, and BLANK signals must be con?gured as outputs.

FIGURE 7.PIXEL AND OVERLAY INPUT TIMING - 16-BIT RGB WITH 2X UPSAMPLING

FIGURE 8.PIXEL AND OVERLAY INPUT TIMING - 24-BIT RGB WITH 2X UPSAMPLING

FIGURE 9.PIXEL AND OVERLAY INPUT TIMING - BT.656

BLANK (INPUT)P0-P15

CLK2

RGB 0RGB 1RGB N

CLK

BLANK (OUTPUT)

OL0-OL2,M1, M0PIXEL 0PIXEL 1PIXEL N

BLANK (INPUT)P0-P24

CLK2

RGB 0RGB 1RGB N

CLK

BLANK (OUTPUT)

Cb 2Y 2Cr 2Y 3Cb 4Y 4CLK2

P8-P15PIXEL 0PIXEL 1OL0-OL2,M1, M0"FF""00"BLANK (OUTPUT)

"00""XY""10"PIXEL N-2PIXEL N-1"10"

"80"PIXEL N

Video Timing Control

The pixel and overlay data must be presented to the HMP8156 at 50 or 59.94 ?elds per second (interlaced). The video timing is controlled by the BLANK,HSYNC,VSYNC,FIELD, and CLK2 pins.

HSYNC,VSYNC, and FIELD Timing

The leading edge of HSYNC indicates the beginning of a horizontal sync interval. If HSYNC is an output, it is asserted for about 4.7μs. If HSYNC is an input, it must be active for at least two CLK2 periods. The width of the horizontal compos-ite sync tip is determined from the video standard and does not depend on the width of HSYNC.

The leading edge of VSYNC indicates the beginning of a vertical sync interval. If VSYNC is an output, it is asserted for 3 scan lines in (M, NSM) NTSC and (M, N) PAL modes or 2.5 scan lines in (B, D, G, H, I, CN) P AL modes. If VSYNC is an input, it must be asserted for at least two CLK2 periods.When HSYNC and VSYNC are con?gured as outputs, their leading edges will occur simultaneously at the start of an odd ?eld. At the start of an even ?eld, the leading edge of VSYNC occurs in the middle of the line.

When HSYNC and VSYNC are con?gured as inputs, if the leading edge of HSYNC occurs within ±127 CLK2 cycles of the leading edge of VSYNC, the encoder assumes it is at the start of an odd ?eld. Otherwise, it assumes it is processing an even ?eld.

The FIELD signal is always an output and changes state near each leading edge of VSYNC. The delay between the syncs and FIELD depends on the encoder’s operating mode as summarized in T able 6. In modes in which the encoder uses CLK to gate its inputs and outputs, the FIELD signal may be delayed 0-12 additional CLK2 periods.

Figure 10 illustrates the HSYNC,VSYNC, and FIELD gen-eral timing for (M, NSM) NTSC and (M, N) P AL. Figure 11illustrates the general timing for (B, D, G, H, I, CN) P AL. In the ?gures, all the signals are shown active low (their reset state), and FIELD is low during odd ?elds.

TABLE 6.FIELD OUTPUT TIMING

OPERATING MODE

CLK2DELAY

COMMENTS

SYNC I/O DIRECTION BLANK I/O DIRECTION Input

Input

148

FIELD lags VSYNC switch-ing from odd to even.FIELD lags the earlier of VSYNC and HSYNC when syncs are aligned when switching from even to odd.Input Output 138FIELD lags VSYNC.Output

Don’t Care

FIELD leads VSYNC.

FIGURE 10A.BEGINNING AN ODD FIELD

FIGURE 10B.BEGINNING AN EVEN FIELD

FIGURE 10.HSYNC,VSYNC, AND FIELD TIMING FOR

(M, NSM) NTSC AND (M, N) PAL

FIGURE 11A.BEGINNING AN ODD FIELD

FIGURE 11B.BEGINNING AN EVEN FIELD

FIGURE 11.HSYNC,VSYNC, AND FIELD TIMING FOR

(B, D, G, H, I, CN) PAL

HSYNC

VSYNC

FIELD

HSYNC

VSYNC

FIELD

HSYNC

VSYNC

FIELD

HSYNC

VSYNC

FIELD

BLANK Timing

The encoder uses the HSYNC,VSYNC, FIELD signals to generate a standard composite video waveform with no active video. The signal includes only sync tips, color burst,and optionally, a 7.5 IRE blanking setup. Based on the BLANK signal, the encoder adds the pixel and overlay input data to the video waveform.

The encoder ignores the pixel and overlay input data when BLANK is asserted. Instead of the input data, the encoder generates the blanking level. The encoder also ignores the pixel and overlay inputs when generating closed captioning data on a speci?c line, even if BLANK is negated.

There must be an even number of active and total pixels per line. In the 8-bit YCbCr modes, the number of active and total pixels per line must be a multiple of four. Note that if BLANK is an output, half-line blanking on the output video cannot be done.

The HMP8156 never adds a 7.5 IRE blanking setup during the active line time on scan lines 1-21 and 263-284 for (M,NSM) NTSC, scan lines 523-18 and 260-281 for (M) P AL,and scan lines 623-22 and 311-335 for (N) P AL, allowing the generation of video test signals, timecode, and other infor-mation by controlling the pixel inputs appropriately.

The relative timing of BLANK,HSYNC, and the output video depends on the blanking and sync I/O directions. The typical timing relation is shown in Figure 12. The delays which vary with operating mode are indicated. The width of the compos-ite sync tip and the location and duration of the color burst are ?xed based on the video format.

When BLANK is an output, the encoder asserts it during the inactive portions of active scan lines and for all of each inac-tive scan line. The inactive scan lines blanked each ?eld are determined by the start_v_blank and end_v_blank registers.The inactive portion of active scan lines is determined by the start_h_blank and end_h_blank registers.

The zero count for horizontal blanking is 32 CLK2 cycles before the 50% point of the composite sync. From this zero point, the HMP8156 counts every other CLK2 cycle. When the count reaches the value in the start_h_blank register, the encoder negates BLANK. When the count reaches the value in the end_h_blank register,BLANK is asserted. There may be an additional 0-7 CLK2 delays in modes which use CLK.The data pipeline delay through the HMP8156 is 26 CLK2cycles. In operating modes which use CLK to gate the inputs into the encoder, the delay may be an additional 0-7 CLK2cycles. The delay from BLANK to the start or end of active video is an additional one-half CLK cycle when the blank tim-ing select bit is cleared. The active video may also appear to end early or start late since the HMP8156 controls the blank-ing edge rates.

The delay from the active edge of HSYNC to the 50% point of the composite sync is 4-39 CLK2 cycles depending on the HMP8156 operating mode. The delay is shortest when the encoder is the timing master; it is longest when in slave mode.CLK2 Input

The CLK2 input clocks all of the HMP8156, including its video timing counters. For proper operation, all of the HMP8156 inputs must be synchronous with CLK2. The fre-quency of CLK2 depends on the device’s operating mode and the total number of pixels per line. The standard clock frequencies are shown in Table 7.

Note that the color subcarrier is derived from the CLK2 input.Any jitter on CLK2 will be transferred to the color subcarrier,resulting in color changes. Just 400ps of jitter on CLK2causes up to a 1o color subcarrier phase shift. Thus, CLK2should be derived from a stable clock source, such as a crystal. The use of a PLL to generate CLK2 is not recom-mended.

FIGURE 12.HSYNC,BLANK, AND OUTPUT VIDEO TIMING

BLANK COMPOSITE VIDEO OUT

HSYNC

SYNC DELAY

START H BLANK DATA PIPE

DELAY

Video Processing

Upsampling

Video processing begins with the 4:4:4 sampled YCbCr data from the input processor. After overlay mixing and optional 2X upscaling, the HMP8156 upsamples the 4:4:4 data to generate 8:8:8 data. The encoder uses linear interpolation for the upsampling.Filtering

If enabled, the HMP8156 lowpass ?lters the Y data to 5.0MHz. Lowpass ?ltering Y removes any aliasing artifacts due to the upsampling process, and simpli?es the analog output ?lters. The Y 5.0MHz lowpass ?lter response is shown in Figure 13. At this point, the HMP8156 also scales the Y data to generate the proper output levels for the vari-ous video standards

The HMP8156 lowpass ?lters the Cb and Cr data to 1.3MHz prior to modulation. The lowpass ?ltering removes any alias-ing artifacts due to the upsampling process (simplifying the analog output ?lters) and also properly bandwidth-limits Cb and Cr prior to modulation. The chrominance ?ltering is not optional like luminance ?ltering. The Cb and Cr 1.3MHz low-pass ?lter response is shown in Figure 14.

TABLE 7.TYPICAL VIDEO TIMING PARAMETERS

VIDEO STANDARD

PIXELS PER LINE

HBLANK REGISTER VALUES VBLANK REGISTER VALUES CLK2(MHZ)

TOTAL

ACTIVE

START

END

START

END

FULL INPUT RESOLUTION, RECTANGULAR PIXELS

(M, NSM) NTSC (B, D, G, H, I) PAL

(M) PAL (N) PAL (CN) PAL

858864858864864

720720720720720

842 (0x34a)853 (0x355)842 (0x34a)853 (0x355)853 (0x355)

122 (0x7a)133 (0x85)122 (0x7a)133 (0x85)133 (0x85)

259 (0x103)310 (0x136)259 (0x103)309 (0x135)310 (0x136)

19 (0x13)22 (0x16)19 (0x13)21 (0x15)22 (0x16)

27.027.027.027.027.0

FULL INPUT RESOLUTION, SQUARE PIXELS

(M, NSM) NTSC (B, D, G, H, I) P AL

(M) PAL (N) PAL (CN) PA L

780944780944944

640768640784768

758 (0x2f6)923 (0x39b)758 (0x2f6)923 (0x39b)923 (0x39b)

118 (0x76)155 (0x9b)118 (0x76)155 (0x9b)155 (0x9b)

259 (0x103)310 (0x136)259 (0x103)309 (0x135)310 (0x136)

19 (0x13)22 (0x16)19 (0x13)21 (0x15)22 (0x16)

24.5429.524.5429.529.5

SIF INPUT RESOLUTION, RECTANGULAR PIXELS

(M, NSM) NTSC (B, D, G, H, I) P AL

(M) PAL (N) PAL (CN) PAL

429432429432432

352352352352352

834 (0x342)845 (0x34d)842 (0x34a)853 (0x355)853 (0x355)

130 (0x82)141 (0x8d)122 (0x7a)133 (0x85)133 (0x85)

259 (0x103)310 (0x136)259 (0x103)309 (0x135)310 (0x136)

19 (0x13)22 (0x16)19 (0x13)21 (0x15)22 (0x16)

27.027.027.027.027.0

SIF INPUT RESOLUTION, SQUARE PIXELS

(M, NSM) NTSC (B, D, G, H, I) PAL

(M) PAL (N) PAL (CN) PAL

390472390472472

320384320392384

758 (0x2f6)923 (0x39b)758 (0x2f6)923 (0x39b)923 (0x39b)

118 (0x76)155 (0x9b)118 (0x76)155 (0x9b)155 (0x9b)

259 (0x103)310 (0x136)259 (0x103)309 (0x135)310 (0x136)

19 (0x13)22 (0x16)19 (0x13)21 (0x15)22 (0x16)

24.5429.524.5429.529.5

FIGURE 13A.FULL SPECTRUM

FIGURE 13.Y LOWPASS FILTER RESPONSE

NTSC SQUARE PIXEL CLK2 = 24.54MHz

NTSC OR PAL

CLK2 = 27.00MHz PAL SQUARE PIXEL CLK2 = 29.50MHz RECTANGULAR PIXEL 0-10-20-30-40-50-60

024********

FREQUENCY (MHz)

A T T E N U A T I O N (d

B )

Chrominance Modulation

The HMP8156 uses a numerically controlled oscillator (NCO)clocked by CLK2 and a sine look up ROM to generate the color subcarrier. The subcarrier from the ROM is pre-scaled to generate the proper levels for the various video standards.Prescaling outside the CbCr data path minimizes color pro-cessing artifacts. The HMP8156 modulates the ?ltered 8:8:8chrominance data with the synthesized subcarrier.Subcarrier Phase

The SCH phase is 0o after reset but then changes monotoni-cally over time due to residue in the NCO. In an ideal sys-tem, zero SCH phase would be maintained forever. In reality,this is impossible to achieve due to pixel clock frequency tol-erances.

If enabled, the HMP8156 resets the NCO periodically to avoid an accumulation of SCH phase error. The reset occurs at the beginning of each ?eld to burst phase sequence. The sequence repeats every 4 ?elds for NTSC or 8 ?elds for PAL.Resetting the SCH phase every four ?elds (NTSC) or eight ?elds (P AL) avoids the accumulation of SCH phase error at the expense of requiring any NTSC/PAL decoder after the encoder be able to handle very minor “jumps” (up to 2o ) in the SCH phase at the beginning of each four-?eld or eight-?eld sequence. Most NTSC/PAL decoders are able to handle this due to video editing https://www.wendangku.net/doc/f311683216.html,posite Video Limiting

The HMP8156 adds the luminance and modulated chromi-nance together with the sync, color burst, and optional blank-ing pedestal to form the composite video data. If enabled in the video processing register, the encoder limits the active video so that it is always greater than one-eighth of full scale.This corresponds to approximately one-half the sync height.This allows the generation of “safe” video in the event non-standard YCbCr values are input to the device.Closed Captioning

If enabled in the auxiliary data control register, the HMP8156generates closed captioning data on speci?ed scan lines.The captioning data stream includes clock run-in and start bits followed by the captioning data. During closed caption-ing encoding, the pixel and overlay inputs are ignored on the scan lines containing captioning information.

The HMP8156 has two 16-bit registers containing the cap-tioning information. Each 16-bit register is organized as two cascaded 8-bit registers. One 16-bit register (caption 21) is read out serially during line 18, 21 or 22; the other 16-bit reg-ister (caption 284) is read out serially during line 281, 284 or 335. The data registers are shifted out LSB ?rst.

The bytes may be written in any order but both must be writ-ten within one frame time for proper operation. If the regis-ters are not updated, the encoder resends the previously loaded values.

FIGURE 14A.FULL SPECTRUM

FIGURE 14B.PASS BAND

FIGURE 14.Cb AND Cr LOWPASS FILTER RESPONSE

FIGURE 13B.PASS BAND

FIGURE 13.Y LOWPASS FILTER RESPONSE

0-0.5-1.0-1.5-2.0-2.5-3.0

A T T E N T U A T I O N (d

B )

FREQUENCY (MHz)

NTSC SQUARE PIXEL CLK2 = 24.54MHz

NTSC OR PAL

CLK2 = 27.00MHz PAL SQUARE PIXEL CLK2 = 29.50MHz

RECTANGULAR PIXEL 01

23456

FREQUENCY (MHz)

-10-20-30

-40

-50-60

A T T E N T U A T I O N (d

B )

NTSC SQUARE PIXEL CLK2 = 24.54MHz

NTSC OR PAL

CLK2 = 27.00MHz RECTANGULAR PIXEL PAL SQUARE PIXEL CLK2 = 29.50MHz

0.2

0.4

0.60.8 1.0 1.2

FREQUENCY (MHz)

0-0.5-1.0-1.5-2.0-2.5-3.0A T T E N T U A T I O N (d B )NTSC SQUARE PIXEL CLK2 = 24.54MHz

NTSC OR PAL

CLK2 = 27.00MHz

RECTANGULAR PIXEL -3.5-4.0

1.4

1.6

PAL SQUARE PIXEL CLK2 = 29.50MHz

The HMP8156 provides a write status bit for each captioning line. The encoder clears the write status bit to ‘0’ when cap-tioning is enabled and both bytes of the captioning data reg-ister have been written. The encoder sets the write status bit to ‘1’ after it outputs the data, indicating the registers are ready to receive new data.

Captioning information may be enabled for either line, both lines, or no lines. The captioning modes are summarized in T able 8.Controlled Edges

The NTSC and PAL video standards specify edge rates and rise and fall times for portions of the video waveform. The HMP8156 automatically implements controlled edge rates and rise and fall times on these edges:

1.Analog horizontal sync (rising and falling edges)

2.Analog vertical sync interval (rising and falling edges)

3.Color burst envelope

4.Blanking of analog active video

5.Overlay with internal mixing

6.Closed captioning information

Analog Outputs

The HMP8156 converts the video data into analog signals using four 10-bit DACs running at the CLK2 rate. The DACs output a current proportional to the digital data. The full scale output current is determined by the reference voltage VREF and an external resistor RSET. The full scale output current is given by

I FULLSCALE(mA) = 3.6 * VREF (V)/RSET (k?)(EQ 1.) VREF must be chosen such that it is within the part’s operat-ing range; RSET must be chosen such that the maximum output current is not exceeded.

If the VREF pin is not connected, the HMP8156 provides an internal reference voltage. Otherwise, the applied voltage overdrives the internal reference. If an external reference is used, it must decoupled from any power supply noise. An example external reference circuit is shown in the Applica-tions section.

The HMP8156 generates 1V PP nominal video signals across 37.5? loads corresponding to doubly terminated 75?lines. The encoder may also drive larger loads. The full scale output current and load must be chosen such that the maxi-mum output voltage is not exceeded.Output DAC Filtering

Since the DACs run at 2x the pixel sample rate, the sin(x)/x rolloff of the outputs is greatly reduced, and there are fewer high frequency artifacts in the output spectrum. This allows using simple analog output ?lters. The analog output ?lter should be ?at to F s/4 and have good rejection at 3F s/4. Example ?lters are shown in the Applications section. Composite + Y/C Output Mode

The HMP8156 provides three output modes: S-video, RGB, and power down. When S-video outputs are selected, the encoder outputs the luminance, modulated chrominance, and two copies of the composite video signals. All four out-puts are time aligned.

To reduce power dissipation, the second composite output DAC may be turned off. The output may be disabled in the host control register.

Composite + RGB Output Mode

When analog RGB video is selected, the HMP8156 trans-forms the ?ltered 8:8:8 YCbCr data into 8:8:8 RGB data. The transform matrix uses ?xed coef?cients to generate P AL video levels for interfacing to a European SCART connector. The encoder will not generate proper video levels if RGB output is selected with NTSC format.

TABLE 8.CLOSED CAPTIONING MODES

CLOSED

CAPTIONING

ENABLE BITS OUTPUT LINE(S)CAPTIONING REGISTER WRITE STATUS BIT 284A

284B

21A

21B28421

00None Ignored Ignored Always 1Always 1

0121 (NTSC)

18 (M PAL)

22 (Other P AL)Ignored Caption Data Always 10 = Loaded

1 = Output

10284 (NTSC)

281 (M P AL)

335 (Other P AL)Caption Data Ignored0 = Loaded

1 = Output

Always 1

1121, 284 (NTSC)

18, 281 (M P AL)

22, 335 (Other PAL)Caption Data Caption Data0 = Loaded

1 = Output

0 = Loaded

1 = Output

The analog RGB outputs have a range of 0.3-1.0V with no blanking pedestal. Composite sync information (0.0-0.3V)may be optionally added to the green output. Closed cap-tioning data is not included on the RGB outputs.

The HMP8156 also generates composite video when in RGB output mode. The analog composite video is output onto the NTSC/P AL 1 pin. Red information is output onto the NTSC/P AL 2 pin, blue information is output onto the C pin,and green information is output onto the Y pin. All four out-puts are time aligned.Power Down Mode

When the power down mode is enabled, all of the DACs are powered down (forcing their outputs to zero) and most of the internal clocks are stopped. The host processor may still read from and write to the internal control registers.

Host Interfaces

Reset

The HMP8156 resets to its default operating mode on power up, when the reset pin is asserted for at least four CLK cycles, or when the software reset bit of the host control reg-ister is set. During the reset cycle, the encoder returns its internal registers to their reset state and deactivates the I 2C interface.I 2C Interface

The HMP8156 provides a standard I 2C interface and sup-ports fast-mode (up to 400 KBPS) transfers. The device acts as a slave for receiving and transmitting data only. It will not respond to general calls or initiate a transfer. The encoder’s slave address is either 0100000x B when the SA input pin is low or 0100001x B when it is high. (The ‘x’ bit in the address is the I 2C read ?ag.)

The I 2C interface consists of the SDA and SCL pins. When the interface is not active, SCL and SDA must be pulled high using external 4-6k ? pull-up resistors. The I 2C clock and data timing is shown in Figures 15 and 16.

FIGURE 15.I 2C SERIAL TIMING FLOW

FIGURE 16.REGISTER WRITE PROGRAMMING FLOW

SDA

SCL

START CONDITION

S 1-7ADDRESS

8R/W

9ACK

1-7

DATA

9ACK

STOP CONDITION

P S = START CYCLE P = STOP CYCLE A = ACKNOWLEDGE

FROM MASTER

FROM HMP8156

0x40 OR DATA WRITE

DATA DATA

DATA READ

NA = NO ACKNOWLEDGE

0x41 OR 0100 000 OR P

CHIP ADDR A

SUB ADDR

DATA DATA

A A

CHIP ADDR S

A SU

B ADDR

CHIP ADDR

0100 0010 0x43

0x42

OPTIONAL FRAME MAY BE REPEATED

n TIMES

OPTIONAL FRAME MAY BE REPEATED

n TIMES

During I2C write cycles, the ?rst data byte after the slave address speci?es the sub address, and is written into the address register. Only the seven LSBs of the subaddress are used; the MSB is ignored. Any remaining data bytes in the I2C write cycle are written to the control registers, beginning with the register speci?ed by the address register. The 7-bit address register is incremented after each data byte in the I2C write cycle. Data written to reserved bits within registers or reserved registers is ignored.

During I2C read cycles, data from the control register speci-?ed by the address register is output. The address register is incremented after each data byte in the I2C read cycle. Reserved bits within registers return a value of “0”. Reserved registers return a value of 00H.

The HMP8156’s operating modes are determined by the contents of its internal registers which are accessed via the I2C interface. All internal registers may be written or read by the host processor at any time. However, some of the bits and words are read only or reserved and data written to these bits is ignored.

T able 9 lists the HMP8156’s internal registers. Their bit descriptions are listed in T ables 10-27.

TABLE 9.CONTROL REGISTER NAMES

SUB ADDRESS

(HEX)CONTROL REGISTER

RESET

CONDITION 00

07-0E

14-1F

26-2F

30-7F

Product ID

Output Format

Input Format

Video Processing

Timing I/O 1

Timing I/O 2

Aux Data Enable

Reserved

Host Control

Closed Caption_21A

Closed Caption_21B

Closed Caption_284A

Closed Caption_284B

Reserved

Start H_Blank Low

Start H_Blank High

End H_Blank

Start V_Blank Low

Start V_Blank High

End V_Blank

Reserved

T est and Unused

56H

00H

06H

A0H

00H

18H

80H

4A H

03H

7A H

03H

01H

13H

TABLE 10.PRODUCT ID REGISTER SUB ADDRESS = 00H

BIT

NUMBER FUNCTION DESCRIPTION RESET STATE

7-0Product ID This 8-bit register specifies the last two digits of the product number. It is a read-only

56H

TABLE 11.OUTPUT FORMAT REGISTER

SUB ADDRESS = 01H

BIT

NUMBER FUNCTION DESCRIPTION RESET STATE

7-5Video Timing

Standard 000 = (M) NTSC

001 = (M) NTSC with a 0 IRE setup; also called (NSM) NTSC

010 = (B, D, G, H, I) PAL

011 = (M) PAL

100 = (N) PAL

101 = combination (N) PAL; also called (CN) PAL

110 = reserved

111 = reserved

000B

4-3Output Format These bits must be set to “00” during (M, NSM) NTSC and (M, N, CN) PAL modes.

00 = Composite + Y/C

01 = reserved

10 = Composite + RGB (no sync on green)

11 = Composite + RGB (with sync on green)

00B 2-0Reserved000B

TABLE 12.INPUT FORMAT REGISTER SUB ADDRESS = 02H

BIT

NUMBER FUNCTION DESCRIPTION RESET STATE

7-5Input Format000 = 16-bit 4:2:2 YCbCr

001 = 8-bit 4:2:2 YCbCr

010 = 8-bit parallel ITU-R BT.656

011 = 16-bit linear RGB

100 = 16-bit gamma-corrected RGB

101 = 24-bit linear RGB

110 = 24-bit gamma-corrected RGB

111 = Blue screen

000B

4Gamma

Select These bits are ignored except during linear RGB input modes.

0 = 1 / 2.2

1 = 1 / 2.8

3Reserved0B

2-1Overlay Mixing

Mode These bits must be set to “11” in 24-bit RGB input modes. Internal mixing should not be selected in BT.656 input mode.

00 = No mixing

01 = Internal mixing

10 = External mixing

11 = Disable overlays

11B

0Input Resolution This bit must be set to “0” during BT.656 input mode.

0 = Full resolution (2x upscaling disabled)

1 = SIF resolution (2x upscaling enabled)

TABLE 13.VIDEO PROCESSING REGISTER

SUB ADDRESS = 03H

BIT

NUMBER FUNCTION DESCRIPTION RESET STATE

7Luminance

Processing 0 = None

1 = Y Lowpass filtering enabled

6Composite Video

Limiting 0 = None

1 = Lower limit of composite active video is about half the sync height

5SCH Phase

Mode 0 = Never reset SCH phase

1 = Reset SCH phase every 4 (NTSC) or 8 (PAL) fields

4-0Reserved00000B

BIT

NUMBER FUNCTION DESCRIPTION RESET STATE

7BLANK

Timing Select This bit is ignored unless BLANK is configured to be an output.

0 = Data for the first active pixel of the scan line must arrive the CLK cycle after the

encoder negates BLANK.

1 = Data for the first active pixel of the scan line must arrive immediately after the encoder negates BLANK.

6Reserved0B

5BLANK Output

Control 0 =BLANK is an input

1 =BLANK is an output

4BLANK

Polarity 0 = Active low (low during blanking)

1 = Active high (high during blanking)

3HSYNC and

VSYNC Output

Control 0 =HSYNC and VSYNC are inputs

1 =HSYNC and VSYNC are outputs

2HSYNC

Polarity 0 = Active low (low during horizontal sync)

1 = Active high (high during horizontal sync)

1VSYNC

Polarity 0 = Active low (low during vertical sync)

1 = Active high (high during vertical sync)

0FIELD

Polarity 0 = Active low (low during odd fields)

1 = Active high (high during odd fields)

TABLE 15.TIMING I/O REGISTER #2

SUB ADDRESS = 05H

BIT

NUMBER FUNCTION DESCRIPTION RESET STATE

7-5Reserved000B 4CLK Output Control0 = CLK is an input

1 = CLK is an output

3Aspect Ratio Mode This bit must be set to “0” during BT.656 input mode.

0 = Rectangular (BT.601) pixels

1 = Square pixels

0B 2-0Reserved00B

TABLE 16.AUXILIARY DATA ENABLE REGISTER

SUB ADDRESS = 06H

BIT

NUMBER FUNCTION DESCRIPTION RESET STATE

7-6Closed Captioning

Enable 00 = Closed caption disabled

01 = Closed caption enabled for odd fields: line 21 for NTSC, line 18 for (M) PAL, or line

22 for (B, D, G, H, I, N, CN) PAL

10 = Closed caption enabled for even fields: line 284 for NTSC, line 281 for (M) PAL, or

line 335 for (B, D, G, H, I, N, CN) PAL

11 = Closed caption enabled for both odd and even fields

00B

5-0Reserved000000B

BIT

NUMBER FUNCTION DESCRIPTION RESET STATE

7Software Reset Setting this bit to “1” initiates a software reset. It is automatically reset to a “0” after the

reset sequence is complete.

6Power Down

Enable 0 = Normal operation

1 = Power down mode

5NTSC/PAL 2

Output Mode 0 = Enabled

1 = Disabled

4Closed Caption

Line 21

Write Status 0 = Caption_21A and Caption_21B data registers contain unused data

1 = Data has been output, host processor may now write to the registers

3Closed Caption

Line 284

Write Status 0 = Caption_284A and Caption_284B data registers contain unused data

1 = Data has been output, host processor may now write to the registers

2-0Reserved000B

TABLE 18.CLOSED CAPTION_21A DATA REGISTER

SUB ADDRESS = 10H

BIT

NUMBER FUNCTION DESCRIPTION RESET STATE

7-0Line 21 Caption

Data

(First Byte)This register is cascaded with the closed caption_21B data register and they are read

out serially as 16 bits during line 18, 21, or 22 if line 21 captioning is enabled. Bit D0 of

the 21A data register is shifted out first.

80H

TABLE 19.CLOSED CAPTION_21B DATA REGISTER

SUB ADDRESS = 11H

BIT

NUMBER FUNCTION DESCRIPTION RESET STATE

7-0Line 21 Caption

Data

(Second Byte)This register is cascaded with the closed caption_21A data register and they are read

out serially as 16 bits during line 18, 21, or 22 if line 21 captioning is enabled. Bit D0 of

the 21A data register is shifted out first.

80H

TABLE 20.CLOSED CAPTION_284A DATA REGISTER

SUB ADDRESS = 12H

BIT

NUMBER FUNCTION DESCRIPTION RESET STATE

7-0Line 284 Caption

Data

(First Byte)This register is cascaded with the closed caption_284B data register and they are read

out serially as 16 bits during line 281, 284, or 335 if line 284 captioning is enabled. Bit

D0 of the 284A data register is shifted out first.

80H

TABLE 21.CLOSED CAPTION_284B DATA REGISTER

SUB ADDRESS = 13H

BIT

NUMBER FUNCTION DESCRIPTION RESET STATE

7-0Line 284 Caption

Data

(Second Byte)This register is cascaded with the closed caption_284A data register and they are read

out serially as 16 bits during line 281, 284, or 335 if line 284 captioning is enabled. Bit

D0 of the 284A data register is shifted out first.

80H

TABLE 22.START H_BLANK LOW REGISTER

SUB ADDRESS = 20H

BIT

NUMBER FUNCTION DESCRIPTION RESET STATE

7-0Assert BLANK

Output Signal

(Horizontal)This 8-bit register is cascaded with Start H_Blank High Register to form a 10-bit

start_horizontal_blank register. It specifies the horizontal count (in 1x clock cycles) at

which to start ignoring pixel data each scan line. The leading edge of HSYNC is count

020H. This register is ignored unless BLANK is configured as an output.

4A H

TABLE 23.START H_BLANK HIGH REGISTER

SUB ADDRESS = 21H

BIT

NUMBER FUNCTION DESCRIPTION RESET STATE

7-2Reserved000000B

1-0Assert BLANK

Output Signal

(Horizontal)This 2-bit register is cascaded with Start H_Blank Low Register to form a 10-bit

start_horizontal_blank register. It specifies the horizontal count (in 1x clock cycles) at

which to start ignoring pixel data each scan line. The leading edge of HSYNC is count

020H. This register is ignored unless BLANK is configured as an output.

11B

TABLE 24.END H_BLANK REGISTER

SUB ADDRESS = 22H

BIT

NUMBER FUNCTION DESCRIPTION RESET STATE

7-0Negate BLANK

Output Signal

(Horizontal)This 8-bit register specifies the horizontal count (in 1x clock cycles) at which to start inputting pixel data each scan line. The leading edge of HSYNC is count 000H. This reg-

ister is ignored unless BLANK is configured as an output.

7A H