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LTC1668中文资料

Information furnished by Linear Technology Corporation is believed to be accurate and reliable.

However, no responsibility is assumed for its use. Linear Technology Corporation makes no represen-tation that the interconnection of its circuits as described herein will not infringe on existing patent rights.

FREQUENCY (1.25MHz/DIV)

0.05

–45–25–51668 G01

–65–85–55–35–15–75–95–105

6.3

12.55

f CLOCK = 25Msps f OUT = 1.007MHz AMPLITUDE = 0dBFS = –8.5dBm SFDR = 86dBc

LTC1668

Consult factory for Military grade parts.

The q denotes specifications which apply over the full operating

temperature range, otherwise specifications are at T A = 25°C. V DD = 5V, V SS = –5V, LADCOM = AGND = DGND = 0V, I OUTFS = 10mA.

(Note 1)

Supply Voltage (V DD )................................................ 6V Negative Supply Voltage (V SS )............................... –6V Total Supply Voltage (V DD to V SS ).......................... 12V Digital Input Voltage ....................–0.3V to (V DD + 0.3V)Analog Output Voltage

(I OUT A and I OUT B )........ (V SS – 0.3V) to (V DD + 0.3V)Power Dissipation............................................. 500mW Operating Temperature Range

LTC1668C .............................................. 0°C to 70°C LTC1668I........................................... –40°C to 85°C Storage Temperature Range................ –65°C to 150°C Lead Temperature (Soldering, 10 sec)..................300°C

PACKAGE/ORDER I FOR ATIO

U U W

ABSOLUTE AXI U RATI GS

W W W

U ELECTRICAL CHARACTERISTICS

LTC1668

TYPICAL PERFOR A CE CHARACTERISTICS

U W

FREQUENCY (1.25MHz/DIV)

0.05

S I G N A L A M P L I T U D E (d B m )

–45–25–51668 G01

–65–85–55–35–15–75–95–105

6.3

12.55

f CLOCK = 25Msps f OUT = 1.007MHz AMPLITUDE = 0dBFS = –8.5dBm SFDR = 86dBc

Single Tone SFDR

2-Tone SFDR

FREQUENCY (0.2MHz/DIV)

3.2

S I G N A L A M P L I T U D E (d B m )

–50–30–101668 G02

–70–90–60–40–20–80–100

–110

4.2

5.2

f CLOCK = 50Msps f OUT1 = 4.028MHz f OUT2

= 4.419MHz

AMPLITUDE 1, 2 = –6dBFS = –14.5dBm SFDR > 77dBc

Integral Nonlinearity

Differential Nonlinearity

DIGITAL INPUT CODE

–5

I N T E G R A L N O N L I N E A R I T Y (L S B )

–4–2–105

216384

327681668 G03

–334

14915265535

DIGITAL INPUT CODE

D I F F

E R E N T I A L N O N L I N E A R I T Y (L S B )

01.065535

1668 G04

–1.0–2.0

163843276849152

2.0–0.50.5–1.51.5U U U

PI FU CTIO S

REFOUT (Pin 15): Internal Reference Voltage Output.Nominal value is 2.5V. Requires a 0.1μF bypass capacitor to AGND.

I REFIN (Pin 16): Reference Input Current. Nominal value is 1.25mA for I FS = 10mA. I FS = I REFIN ? 8.AGND (Pin 17): Analog Ground.

LADCOM (Pin 18): Attenuator Ladder Common. Normally tied to GND.

I OUT B (Pin 19): Complementary DAC Output Current. Full-scale output current occurs when all data bits are 0s.I OUT A (Pin 20): DAC Output Current. Full-scale output current occurs when all data bits are 1s.

COMP1 (Pin 21): Current Source Control Amplifier Com-pensation. Bypass to V SS with 0.1μF.

COMP2 (Pin 22): Internal Bypass Point. Bypass to V SS with 0.1μF.

V SS (Pin 23): Negative Supply Voltage. Nominal value is –5V.

DGND (Pin 24): Digital Ground.

V DD (Pin 25): Positive Supply Voltage. Nominal value is 5V.CLK (Pin 26): Clock Input. Data is latched and the output is updated on positive edge of clock.

DB15 to DB0 (Pins 27, 28, 1 to 14): Digital Input Data Bits.

LTC1668

APPLICATIO S I FOR ATIO

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U Theory of Operation

The LTC1668 is a high speed current steering 16-Bit DAC made on an advanced BiCMOS process. Precision thin film resistors and well matched bipolar transistors result in excellent DC linearity and stability. A low glitch current switching design gives excellent AC performance at sample rates up to 50Msps. The device is complete with a 2.5V internal bandgap reference and edge triggered latches,and sets a new standard for DAC applications requiring very high dynamic range at output frequencies up to several megahertz.

Referring to the Block Diagram, the DAC contains an array of current sources that are steered to I OUTA or I OUTB with NMOS differential current switches. The four most signifi-cant bits, DB15 to DB12 are made up of 15 current segments of equal weight. The lower bits, DB11 to DB0 are binary weighted, using a combination of current scaling and a differential resistive attenuator ladder. All bits and segments are precisely matched, both in current weight for DC linearity, and in switch timing for low glitch impulse and low spurious tone AC performance.Setting the Full-Scale Current, I OUTFS

The full-scale DAC output current, I OUTFS , is nominally 10mA, and can be adjusted down to 1mA. Placing a resistor, R SET , between the REFOUT pin, and the I REFIN pin sets I OUTFS as follows.

The internal reference control loop amplifier maintains a virtual ground at I REFIN by servoing the internal current source, I INT , to sink the exact current flowing into I REFIN .I INT is a scaled replica of the DAC current sources and I OUTFS = 8 ? (I INT ), therefore:

I OUTFS = 8 ? (I REFIN ) = 8 ? (V REF /R SET )

(1)

For example, if R SET = 2k and is tied to V REF = REFOUT =2.5V, I REFIN = 2.5/2k = 1.25mA and I OUTFS = 8 ? (1.25mA)= 10mA.

The reference control loop requires a capacitor on the COMP1 pin for compensation. For optimal AC perfor-mance, C COMP1 should be connected to V SS and be placed very close to the package (less than 0.1").

For fixed reference voltage applications, C COMP1 should be 0.1μF or more. The reference control loop small-signal bandwidth is approximately 1/(2π) ? C COMP1 ? 80 or 20kHz for C COMP1 = 0.1μF.

Internal Reference Output—REFOUT

The onboard 2.5V bandgap voltage reference drives the REFOUT pin. It is trimmed and specified to drive a 2k resistor tied from REFOUT to I REFIN , corresponding to a 1.25mA load (I OUTFS = 10mA). REFOUT has nominal output impedance of 6?, or 0.24% per mA, so it must be buffered to drive any additional external load. A 0.1μF capacitor is required on the REFOUT pin for compensa-tion. Note that this capacitor is required for stability, even if the internal reference is not being used.DAC Transfer Function

The LTC1668 uses straight binary digital coding. The complementary current outputs, I OUT A and I OUT B , sink current from 0 to I OUTFS . For I OUTFS = 10mA (nominal),I OUT A swings from 0mA when all bits are low (i.e., Code =0) to 10mA when all bits are high (i.e., Code = 65535) (deci-mal representation). I OUT B is complementary to I OUT A .I OUT A and I OUT B are given by the following formulas:I OUT A = I OUTFS ? (DAC Code/65536)(2)I OUT B = I OUTFS ? (65535-DAC Code)/65536

(3)

In typical applications, the LTC1668 differential output currents either drive a resistive load directly or drive an equivalent resistive load through a transformer, or as the feedback resistor of an I-to-V converter. The voltage outputs generated by the I OUT A and I OUT B output currents are then:

V OUT A = I OUT A ? R LOAD (4)V OUT B = I OUT B ? R LOAD (5)

The differential voltage is:V DIFF = V OUT A – V OUT B

(6) = (I OUT A – I OUT B ) ? (R LOAD )

LTC1668

APPLICATIO S I FOR ATIO

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U accuracy improves rapidly, roughly in proportion to 1/I OUTFS . The AC performance tends to be less affected by reducing I OUTFS , except for the unavoidable affects on SFDR and THD due to increased INL and DNL.Output Configurations

Based on the specific application requirements, the LTC1668 allows a choice of the best of several output configurations. Voltage outputs can be generated by ex-ternal load resistors, transformer coupling or with an op amp I-to-V converter. Single-ended DAC output configu-rations use only one of the outputs, preferably I OUT A , to produce a single-ended voltage output. Differential mode configurations use the difference between I OUT A and I OUT B to generate an output voltage, V DIFF , as shown in equation 7. Differential mode gives much better accuracy in most AC applications. Because the DAC chip is the point of interface between the digital input signals and the analog output, some small amount of noise coupling to I OUT A and I OUT B is unavoidable. Most of that digital noise is common mode and is canceled by the differential mode circuit. Other significant digital noise components can be modeled as V REF or I OUTFS noise. In single-ended mode,

I OUTFS noise is gone at zero scale and is fully present at full scale. In differential mode, I OUTFS noise is cancelled at midscale input, corresponding to zero analog output.Many AC signals, including broadband and multitone communications signals with high peak to average ratios,stay mostly near midscale.

Differential transformer-coupled output configurations usually give the best AC performance. An example is the AC Characterization Setup circuit, Figure 2. The advan-tages of transformer coupling include excellent rejection of common mode distortion and noise over a broad frequency range and convenient differential-to-single-ended conversion with isolation or level shifting. Also, as much as twice the power can be delivered to the load, and impedance matching can be accomplished by selecting the appropriate transformer turns ratio. The center tap on the primary side of the transformer is tied to ground to provide the DC current path for I OUT A and I OUT B . For low distortion, the DC average of the I OUT A and I OUT B currents must be exactly equal to avoid biasing the core. This is especially important for compact RF transformers with small cores. The circuit in Figure 2 uses a Mini-Circuits T1-1T RF transformer with a 1:1 turns ratio. The load

0.1μLOW JITTER CLOCK SOURCE

0.1μTO HP3589A SPECTRUM ANALYZER 50? INPUT

Figure 2. AC Characterization Setup

LTC1668

APPLICATIO S I FOR ATIO

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U cause phase modulation of the clock signal and the DAC waveform, and can produce spurious tones. It is normally best to place the digital data transitions near the falling clock edge, well away from the active rising clock edge.Because the clock signal contains spectral components only at the sampling frequency and its multiples, it is usually not a source of in band spurious tones. Overall, it is better to treat the clock as you would an analog signal and route it separately from the digital data input signals.The clock trace should be routed either over the analog ground plane or over its own section of the ground plane.The clock line needs to have accurately controlled imped-ance and should be well terminated near the LTC1668.Printed Circuit Board Layout Considerations—Grounding, Bypassing and Output Signal Routing The close proximity of high frequency digital data lines and high dynamic range, wide-band analog signals makes clean printed circuit board design and layout an absolute necessity. Figures 5 to 9 are the printed circuit board layers for an AC evaluation circuit for the LTC1668. Ground planes should be split between digital and analog sections as shown. All bypass capacitors should have minimum trace length and be ceramic 0.1μF or larger with low ESR.

Bypass capacitors are required on V SS , V DD and REFOUT,and all connected to the AGND plane. The COMP2 pin ties to a node in the output current switching circuitry, and it requires a 0.1μF bypass capacitor. It should be bypassed to V SS along with COMP1. The AGND and DGND pins should both tie directly to the AGND plane, and the tie point between the AGND and DGND planes should nominally be near the DGND pin. LADCOM should either be tied directly to the AGND plane or be bypassed to AGND. The I OUT A and I OUT B traces should be close together, short, and well matched for good AC CMRR. The transformer output ground should be capable of optionally being isolated or being tied to the AGND plane, depending on which gives better performance in the system.Suggested Evaluation Circuit

Figure 4 is the schematic and Figures 5 to 9 are the circuit board layouts for a suggested evaluation circuit, DC245A.The circuit can be programmed with component selection and jumpers for a variety of differentially coupled trans-former output and differential and single-ended resistor loaded output configurations.

LTC1668

APPLICATIO S I FOR ATIO

Figure 5. Suggested Evaluation Circuit Board—Silkscreen

Figure 6. Suggested Evaluation Circuit Board—Component Side

LTC1668

APPLICATIO S I FOR ATIO

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U U

Figure 9. Suggested Evaluation Circuit Board—Solder Side

LTC1668

? Linear Technology Corporation

1630 McCarthy Blvd., Milpitas, CA 95035-7417

(408) 432-1900 q F AX: (408) 434-0507 q https://www.wendangku.net/doc/f012657501.html,

PART NUMBER DESCRIPTION COMMENTS

LTC14068-Bit, 20Msps ADC Undersampling Capability Up to 70MHz Input LTC141414-Bit, 2.2Msps ADC 84dB SFDR at 1.1MHz f IN LTC142012-Bit, 10Msps ADC 72dB SINAD at 5MHz f IN

LTC1604

16-Bit, 333ksps ADC

16-Bit, No Missing Codes, 90dB SINAD, –100dB THD

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TYPICAL APPLICATIO

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0.1μ0.1μF

OUT 1V