M41T94MH6F中文资料
November 2007 Rev 51/41
M41T94
Serial real-time clock with 44 bytes NVRAM and reset
Features
■Counters for tenths/hundredths of seconds, seconds, minutes, hours, day, date, month, year, and century
■
32KHz crystal oscillator integrating load capacitance (12.5pF) providing exceptional oscillator stability and high crystal series resistance operation
■Serial peripheral interface (2MHz SPI)■Ultra-low battery supply current of 500nA (max)■ 2.7 to 5.5V operating voltage
■ 2.5 to 5.5V oscillator operating voltage ■Battery low flag
■Automatic switchover and deselect circuitry ■44 bytes of general purpose RAM
■Programmable alarm and interrupt function (valid even during battery back-up mode)■Accurate programmable watchdog timer (from 62.5ms to 128s)
■Microprocessor power-on reset ■
Choice of power-fail deselect voltages (V CC = 2.7 to 5.5V):
–THS = V SS ; 2.55V ≤ V PFD ≤ 2.70V –THS = V CC ; 4.20V ≤ V PFD ≤ 4.50V ■
Packaging includes a 28-lead SOIC and
SNAPHAT ? top (to be ordered separately) or 16-lead SOIC
■
28-lead SOIC package provides direct
connection for a SNAPHAT top which contains the battery and crystal
■
RoHS compliant
–Lead-free second level interconnect
https://www.wendangku.net/doc/f712998052.html,
Contents M41T94
Contents
1Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
2Signal description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
2.1Serial data output (SDO) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
2.2Serial data input (SDI) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
2.3Serial clock (SCL) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
2.4Chip enable (E) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
3Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
3.1SPI bus characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
3.2Read and write cycles . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
3.3Data retention mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
4Clock operations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
4.1Power-down time-stamp . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
4.2Clock registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
4.3Setting alarm clock registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
4.4Watchdog timer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
4.5Square wave output . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
4.6Power-on reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
4.7Reset inputs (RSTIN1 & RSTIN2) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
4.8Calibrating the clock . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24
4.9Century bit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26
4.10Output driver pin . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27
4.11Battery low warning . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27
4.12t REC bit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27
4.13Initial power-on defaults . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28 5Maximum rating . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29 6DC and AC parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30 7Package mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33 2/41
M41T94Contents 8Part numbering . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38 9References . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39 10Revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40
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List of figures M41T94 List of figures
Figure 1.Logic diagram. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 Figure 2.16-pin SOIC connections . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 Figure 3.28-pin SOIC connections . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 Figure 4.Block diagram. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 Figure 5.Hardware hookup. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 Figure 6.Data and clock timing. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 Figure 7.Input timing requirements. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 Figure 8.Output timing requirements . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 Figure 9.Read mode sequence. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 Figure 10.Write mode sequence. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 Figure 11.Alarm interrupt reset waveforms. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 Figure 12.Back-up mode alarm waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 Figure 13.RSTIN1 and RSTIN2 timing waveforms. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 Figure 14.Crystal accuracy across temperature. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26 Figure 15.Calibration waveform . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26 Figure 16.AC testing input/output waveforms. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30 Figure 17.Power down/up mode AC waveforms. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32 Figure 18.SO16 – 16-lead plastic small outline package outline . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34 Figure 19.SOH28 – 28-lead plastic small outline, battery SNAPHAT, package outline . . . . . . . . . . . 35 Figure 20.SH – 4-pin SNAPHAT housing for 48mAh battery & crystal, package outline . . . . . . . . . . 36 Figure 21.SH – 4-pin SNAPHAT housing for 120mAh battery & crystal, package outline . . . . . . . . . 37 4/41
M41T94List of tables List of tables
Table 1.Signal names . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 Table 2.Function table. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 Table 3.AC characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 Table 4.Clock register map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 Table 5.Alarm repeat mode. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 Table 6.Square wave output frequency. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 Table 7.Reset AC characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 Table 8.t REC definitions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28 Table 9.Default values. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28 Table 10.Absolute maximum ratings. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29 Table 11.DC and AC measurement conditions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30 Table 12.Capacitance . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30 Table 13.DC characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31 Table 14.Crystal electrical characteristics (externally supplied) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31 Table 15.Power down/up AC characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32 Table 16.SO16 – 16-lead Plastic small outline package mechanical data . . . . . . . . . . . . . . . . . . . . 34 Table 17.SOH28 – 28-lead plastic small outline, battery SNAPHAT, package mechanical data . . . 35 Table 18.SH – 4-pin SNAPHAT housing for 48mAh battery & crystal, package mechanical data . . 36 Table 19.SH – 4-pin SNAPHAT housing for 120mAh battery & crystal, package mech. data. . . . . . 37 Table 20.Ordering information scheme. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38 Table 21.SNAPHAT battery table . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38 Table 22.Document revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40
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Description M41T94 1 Description
The M41T94 is a serial real-time clock with 44 bytes of NVRAM and a RESET output. A
built-in 32,768Hz oscillator (external crystal controlled) and 8 bytes of the SRAM (see
Table4 on page19) are used for the clock/calendar function and are configured in binary
coded decimal (BCD) format.
An additional 12 bytes of RAM provide status/control of Alarm, Watchdog and Square Wave
functions. Addresses and data are transferred serially via a serial SPI interface. The built-in
address register is incremented automatically after each WRITE or READ data byte. The
M41T94 has a built-in power sense circuit which detects power failures and automatically
switches to the battery supply when a power failure occurs. The energy needed to sustain
the SRAM and clock operations can be supplied by a small lithium button-cell supply when a
power failure occurs. Functions available to the user include a non-volatile, time-of-day
clock/calendar, Alarm interrupts, Watchdog timer and programmable Square Wave output.
Other features include a Power-On reset as well as two additional debounced inputs
address locations contain the century, year, month, date, day, hour, minute, second and
tenths/hundredths of a second in 24 hour BCD format. Corrections for 28, 29 (leap year -
valid until year 2100), 30 and 31 day months are made automatically. The ninth clock
address location controls user access to the clock information and also stores the clock
software calibration setting.
The M41T94 is supplied in either a 16-lead plastic SOIC (requiring user supplied crystal and
battery) or a 28-lead SOIC SNAPHAT? package (which integrates both crystal and battery
in a single SNAPHAT top). The 28-pin, 330mil SOIC provides sockets with gold plated
contacts at both ends for direct connection to a separate SNAPHAT housing containing the
battery and crystal. The unique design allows the SNAPHAT battery/crystal package to be
mounted on top of the SOIC package after the completion of the surface mount process.
Insertion of the SNAPHAT housing after reflow prevents potential battery and crystal
damage due to the high temperatures required for device surface-mounting. The SNAPHAT
housing is also keyed to prevent reverse insertion.
The SOIC and battery/crystal packages are shipped separately in plastic anti-static tubes or
in T ape & Reel form. For the 28-lead SOIC, the battery/crystal package (e.g., SNAPHAT)
part number is “M4TXX-BR12SH” (see Table21 on page38).
Caution:Do not place the SNAPHAT battery/crystal top in conductive foam, as this will drain the lithium button-cell battery.
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M41T94Description
1.For SO16 package only.
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Description M41T94
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Table 1.Signal names
E Chip enable
IRQ/FT/OUT
Interrupt/frequency test/out
output (open drain)
RST Reset output (open drain) RSTIN1Reset 1 input
RSTIN2Reset 2 input
SCL Serial clock input
SDI Serial data input
SDO Serial data output
SQW Square wave output
THS Threshold select pin
WDI Watchdog input
XI (1)
1.For SO16 package only.
Oscillator input
XO (1)Oscillator output
V BA T (1)Battery supply voltage
V CC Supply voltage
V SS Ground
M41T94Description
1.Open drain output
1.CPOL (clock polarity) and CPHA (clock phase) are bits that may be set in the SPI control register of the MCU.
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Description M41T94
1.SDO remains at High Z until eight bits of data are ready to be shifted out during a READ.
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M41T94
Signal description
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2 Signal description
2.1
Serial data output (SDO)
The output pin is used to transfer data serially out of the Memory. Data is shifted out on the
falling edge of the serial clock.
2.2 Serial data input (SDI)
The input pin is used to transfer data serially into the device. Instructions, addresses, and the data to be written, are each received this way. Input is latched on the rising edge of the serial clock.
2.3 Serial clock (SCL)
The serial clock provides the timing for the serial interface (as shown in Figure 7 on page 13 and Figure 8 on page 14). The W/R bit, addresses, or data are latched, from the input pin, on the rising edge of the clock input. The output data on the SDO pin changes state after the falling edge of the clock input.
The M41T94 can be driven by a microcontroller with its SPI peripheral running in either of the two following modes:
●(CPOL, CPHA) = ('0', '0') or ●
(CPOL, CPHA) = ('1', '1').
For these two modes, input data (SDI) is latched in by the low-to-high transition of clock SCL, and output data (SDO) is shifted out on the high-to-low transition of SCL (see Table 2 on page 10 and Figure 6 on page 10).
2.4 any operation.
Operation M41T94 3 Operation
The M41T94 clock operates as a slave device on the SPI serial bus. Each memory device is
accessed by a simple serial interface that is SPI bus compatible. The bus signals are SCL,
SDI and SDO (see T able1 on page8 and Figure5 on page9). The device is selected when
in and out of the chip. The most significant bit is presented first, with the data input (SDI)
64 bytes contained in the device can then be accessed sequentially in the following order:
●1st byte: tenths/hundredths of a second register
●2nd byte: seconds register
●3rd byte: minutes register
●4th byte: century/hours register
●5th byte: day register
●6th byte: date register
●7th byte: month register
●8th byte: year register
●9th byte: control register
●10th byte: watchdog register
●11th - 16th bytes: Alarm registers
●17th - 19th bytes: reserved
●20th byte: square wave register
●21st - 64th bytes: user RAM
The M41T94 clock continually monitors V CC for an out-of tolerance condition. Should V CC
fall below V PFD, the device terminates an access in progress and resets the device address
counter. Inputs to the device will not be recognized at this time to prevent erroneous data
from being written to the device from a an out-of-tolerance system. When V CC falls below
V SO, the device automatically switches over to the battery and powers down into an ultra low
current mode of operation to conserve battery life. As system power returns and V CC rises
above V SO, the battery is disconnected, and the power supply is switched to external V CC.
Write protection continues until V CC reaches V PFD(min) plus t REC (min). For more
information on Battery Storage Life refer to Application Note AN1012.
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M41T94
Operation
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3.1 SPI bus characteristics
The Serial Peripheral interface (SPI) bus is intended for synchronous communication
between different ICs. It consists of four signal lines: Serial data input (SDI), Serial data output (SDO), Serial clock (SCL) and a Chip Enable (E).
By definition a device that gives out a message is called “transmitter,” the receiving device that gets the message is called “receiver.” The device that controls the message is called “master.” The devices that are controlled by the master are called “slaves.”
The E input is used to initiate and terminate a data transfer. The SCL input is used to synchronize data transfer between the master (micro) and the slave (M41T94) devices.The SCL input, which is generated by the microcontroller, is active only during address and data transfer to any device on the SPI bus (see Figure 5 on page 9).
The M41T94 can be driven by a microcontroller with its SPI peripheral running in either of the two following modes:
●(CPOL, CPHA) = ('0', '0') or ●
(CPOL, CPHA) = ('1', '1').
For these two modes, input data (SDI) is latched in by the low-to-high transition of clock SCL, and output data (SDO) is shifted out on the high-to-low transition of SCL (see Table 2 on page 10 and Figure 6 on page 10).
There is one clock for each bit transferred. Address and data bits are transferred in groups of eight bits. Due to memory size the second most significant address bit is a Don’t Care (address bit 6).
Operation M41T94
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M41T94
Operation
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Table 3.
AC characteristics
Symbol Parameter (1)
1.Valid for ambient operating temperature: T A = –40 to 85°C; V CC =
2.7 to 5.5V (except where noted).Min Max Unit f SCL Serial clock input frequency DC 2
MHz t CH (2)2.t CH + t CL ≥ 1/f SCL
Clock high
200
ns t CHCL (3)3.Value guaranteed by design, not 100% tested in production.
Clock transition (fall time)
1μs t CHDX Serial clock input high to input data transition 50ns t CHEH Serial clock input high to chip enable high 200ns t CL (2)Clock low
200
ns t CLCH (3)Clock transition (rise time)
1μs t CLQV Serial clock input low to output valid
150
ns t CLQX Serial clock input low to output data transition 0
ns t DHDL (3)Input data transition (fall time)1μs t DLDH (3)Input data transition (rise time)1
μs t DVCH Input data to serial clock input high 40ns t EHCH Chip enable high to serial clock input high 200ns t EHEL Chip enable high to chip enable low 200
ns t EHQZ (3)Chip enable high to output high-z 250
ns t ELCH Chip enable low to serial clock input high 200
ns t QHQL (3)Output data transition (fall time)100ns t QLQH (3)
Output data transition (rise time)
100
ns
Operation
M41T94
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3.2 Read and write cycles
Address and data are shifted MSB first into the Serial Data Input (SDI) and out of the Serial Data Output (SDO). Any data transfer considers the first bit to define whether a READ or WRITE will occur. This is followed by seven bits defining the address to be read or written. Data is transferred out of the SDO for a READ operation and into the SDI for a WRITE operation. The address is always the second through the eighth bit written after the Enable (E) pin goes low. If the first bit is a '1,' one or more WRITE cycles will occur. If the first bit is a '0,' one or more READ cycles will occur (see Figure Figure 9 on page 17 and Figure 10 on page 17).
Data transfers can occur one byte at a time or in multiple byte burst mode, during which the address pointer will be automatically incremented. For a single byte transfer, one byte is read or written and then E is driven high. For a multiple byte transfer all that is required is that E continue to remain low. Under this condition, the address pointer will continue to increment as stated previously. Incrementing will continue until the device is deselected by taking E high. The address will wrap to 00h after incrementing to 3Fh.
The system-to-user transfer of clock data will be halted whenever the address being read is a clock address (00h to 07h). Although the clock continues to maintain the correct time, this will prevent updates of time and date during either a READ or WRITE of these address locations by the user. The update will resume either due to a deselect condition or when the pointer increments to an non-clock or RAM address (08h to 3Fh).
Note:This is true both in READ and WRITE mode.
3.3 Data retention mode
With valid V CC applied, the M41T94 can be accessed as described above with READ or
WRITE cycles. Should the supply voltage decay, the M41T94 will automatically deselect, write protecting itself when V CC falls between V PFD (max) and V PFD (min) (see Figure 17 on page 32CC returns to nominal levels. When V CC falls below the switch-over voltage (V SO ), power input is switched from the V CC pin to the SNAPHAT battery (or external battery for SO16) at this time, and the clock registers are maintained from the attached battery supply. All outputs become high impedance. On power up, when V CC returns to a nominal value, write
protection continues for t REC during this time (see Figure 17 on page 32). Before the next active cycle, Chip Enable should be taken high for at least t EHEL , then low.
For a further more detailed review of battery lifetime calculations, please see Application Note AN1012.
M41T94Operation
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Clock operations
M41T94
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4 Clock operations
The eight byte clock register (see Table 4 on page 19) is used to both set the clock and to
read the date and time from the clock, in a binary coded decimal format. Tenths/Hundredths of Seconds, Seconds, Minutes, and Hours are contained within the first four registers. Bits D6 and D7 of clock register 03h (century/hours register) contain the CENTURY ENABLE bit (CEB) and the CENTURY bit (CB). Setting CEB to a '1' will cause CB to toggle, either from '0' to '1' or from '1' to '0' at the turn of the century (depending upon its initial state). If CEB is set to a '0,' CB will not toggle. Bits D0 through D2 of register 04h contain the Day (day of week). Registers 05h, 06h, and 07h contain the Date (day of month), Month and Y ears. The ninth clock register is the Control register (this is described in the clock calibration section). Bit D7 of register 01h contains the STOP bit (ST). Setting this bit to a '1' will cause the
oscillator to stop. If the device is expected to spend a significant amount of time on the shelf, the oscillator may be stopped to reduce current drain. When reset to a '0' the oscillator restarts within one second.
The eight clock registers may be read one byte at a time, or in a sequential block. The
Control register (Address location 08h) may be accessed independently. Provision has been made to assure that a clock update does not occur while any of the eight clock addresses are being read. If a clock address is being read, an update of the clock registers will be halted. This will prevent a transition of data during the READ.
4.1 Power-down time-stamp
When a power failure occurs, the Halt Update bit (HT) will automatically be set to a '1.' This
will prevent the clock from updating the clock registers, and will allow the user to read the exact time of the power-down event. Resetting the HT bit to a '0' will allow the clock to
update the clock registers with the current time. For more information, see Application Note AN1572.
4.2 Clock registers
The M41T94 offers 20 internal registers which contain clock, Alarm, Watchdog, Flag,
Square Wave and Control data (see Table 4 on page 19). These registers are memory locations which contain external (user accessible) and internal copies of the data (usually referred to as BiPORT ? cells). The external copies are independent of internal functions except that they are updated periodically by the simultaneous transfer of the incremented internal copy. The internal divider (or clock) chain will be reset upon the completion of a WRITE to any clock address.
The system-to-user transfer of clock data will be halted whenever the clock addresses (00h to 07h) are being written. The update will resume either due to a deselect condition or when the pointer increments to a non-clock or RAM address.
Clock and Alarm registers store data in BCD. Control, Watchdog and Square Wave registers store data in Binary format.
M41T94
Clock operations
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Table 4.
Clock register map (1)
1.Keys:
S = Sign bit
FT = Frequency test bit ST = Stop bit
0 = Must be set to zero
BL = Battery low flag (read only)
BMB0-BMB4 = Watchdog multiplier bits CEB = Century enable bit CB = Century bit OUT = Output level
AFE = Alarm flag enable flag
RB0-RB1 = Watchdog resolution bits WDS = Watchdog steering bit
ABE = Alarm in battery back-up mode enable bit RPT1-RPT5 = Alarm repeat mode bits WDF = Watchdog flag (read only)WDF = Watchdog flag (read only)AF = Alarm flag (read only)SQWE = Square wave enable RS0-RS3 = SQW frequency HT = Halt update bit TR = t REC bit
Addr Function/range BCD format D7
D6
D5D4
D3
D2
D1
D0
00h 0.1 seconds
0.01 seconds Seconds 00-9901h ST 10 seconds Seconds Seconds 00-5902h 010 minutes
Minutes
Minutes
00-59
03h CEB CB 10 Hours Hours (24 hour format)Century/hours 0-1/00-23
04h TR 00
Day of week
Day 01-705h 0010 date
Date: day of month
Date 01-3106h 0
0010M Month Month 01-1207h 10 Y ears
Y ear
Y ear 00-99
08h OUT FT S Calibration
Control 09h WDS BMB4BMB3BMB2BMB1BMB0
RB1
RB0
Watchdog 0Ah AFE SQWE ABE
Al 10M
Alarm month Al month 01-120Bh RPT4RPT5
AI 10 date Alarm date Al date
01-310Ch RPT3HT
AI 10 hour
Alarm hour Al hour 00-230Dh RPT2Alarm 10 minutes Alarm minutes Al min 00-590Eh RPT1Alarm 10 seconds Alarm seconds Al sec 00-590Fh WDF AF 0BL 0000
Flags 10h 00000000Reserved 11h 00000000Reserved 12h 00000000Reserved 13h
RS3RS2
RS1
RS0
SQW
Clock operations M41T94
4.3 Setting alarm clock registers
Address locations 0Ah-0Eh contain the Alarm settings. The Alarm can be configured to go
off at a prescribed time on a specific month, date, hour, minute, or second, or repeat every
year, month, day, hour, minute, or second. It can also be programmed to go off while the
M41T94 is in the battery back-up to serve as a system wake-up call.
Bits RPT5-RPT1 put the Alarm in the Repeat mode of operation. Table5 on page20 shows
the possible configurations. Codes not listed in the table default to the once per second
mode to quickly alert the user of an incorrect Alarm setting.
When the clock information matches the Alarm clock settings based on the match criteria
defined by RPT5-RPT1, the AF (Alarm Flag) is set. If AFE (Alarm Flag Enable) is also set,
the Alarm condition activates the IRQ/FT/OUT pin.
Note:I f the address pointer is allowed to increment to the Flag register address, an Alarm condition will not cause the Interrupt/Flag to occur until the address pointer is moved to a
different address. It should also be noted that if the last address written is the “Alarm
Seconds,” the address pointer will increment to the Flag address, causing this situation to
occur.
To disable the Alarm, write '0' to the Alarm date register and to RPT1–5. The IRQ/FT/OUT
output is cleared by a READ to the Flags register. This READ of the Flags register will also
reset the Alarm Flag (D6; register 0Fh). See Figure11 on page21.
The IRQ/FT/OUT pin can also be activated in the Battery Back-up mode. The IRQ/FT/OUT
will go low if an Alarm occurs and both ABE (Alarm in Battery Back-up mode Enable) and
AFE are set. The ABE and AFE bits are reset during power-up, therefore an Alarm
generated during power-up will only set AF. The user can read the Flag register at system
boot-up to determine if an Alarm was generated while the M41T94 was in the deselect
mode during power-up. Figure12 on page21 illustrates the Back-up mode Alarm timing.
Table 5.Alarm repeat mode
RPT5RPT4RPT3RPT2RPT1Alarm setting
11111Once per second
11110Once per minute
11100Once per hour
11000Once per day
10000Once per month
00000Once per year
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