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ST6381中文资料

October 20031/82

ST6380, S T6381, S T6382,ST6383, S T6388, S T6389

8-BIT MCUs WITH

ON-SCREEN-DISPLAY FOR TV TUNING

s 4.5 to 6V supply operating range s 8MHz Maximum Clock Frequency

s User Program ROM: up to 20140 bytes s Reserved Test ROM: up to 340 bytes s Data ROM: user selectable size s Data RAM: 256 bytes s Data EEPROM: 384 bytes

s 42-Pin Shrink Dual in Line Plastic Package s

Up to 22 software programmable general purpose Inputs/Outputs, including 2 direct LED driving Outputs

Two Timers each including an 8-bit counter with a 7-bit programmable prescaler s Digital Watchdog Function

Serial Peripheral Interface (SPI) supporting S-BUS/ I 2 C BUS and standard serial protocols s SPI for external frequency synthesis tuning s 14-bit counter for voltage synthesis tuning s Up to Six 6-Bit PWM D/A Converters

s One 8 bits D/A Converter with 7 analog inputs s

Five interrupt vectors (IRIN/NMI, Timer 1 & 2,VSYNC, PWR /ADC)s On-chip clock oscillator

8 Lines by 20 Characters On-Screen Display Generator with 192 Characters in one bank.14X18 OSD characters with rounding function.s

All ROM types are supported by pin-to-pin EPROM and OTP versions with programmable OSD fonts.

The development tool of the ST6380, 81, 82,83, 88 and ST6389 microcontrollers consists of the ST638X-EMU2 emulation and development system to be connected via a standard parallel line to an MS-DOS Personal Computer.

DEVICE SUMMARY

DEVICE ROM (Bytes)D/A Converter

ST63808K 6ST63818K 4ST638216K 6ST638316K 4ST638820K 6ST6389

20K

PSDIP42

(Refer to end of Document for Ordering Information)

ST6380, ST6381, ST6382, ST6383, ST6388, ST6389 . . . . . . . .1

1 GENERAL DESCRIPTION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5

1.1INTRODUCTION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5

1.2PIN DESCRIPTION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7

1.3MEMORY SPACES . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9

1.3.1Stack Space . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9

1.3.2Program Space . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9

1.3.3Data Space . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11

1.3.4Data RAM/EEPROM/OSD RAM Addressing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13

2 CENTRAL PROCESSING UNIT . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16

2.1INTRODUCTION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16

2.2CPU REGISTERS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16

3 CLOCKS, RESET, INTERRUPTS AND POWER SAVING MODES . . . . . . . . . . . . . . . . . . . . . 18

3.1ON-CHIP CLOCK OSCILLATOR . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18

3.2RESETS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19

3.2.1RESET Input . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19

3.2.2Power-on Reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19

3.2.3Watchdog Reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20

3.2.4Application Note . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20

3.2.5MCU Initialization Sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20

3.3POWER SAVING MODES . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21

3.3.1WAIT Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21

3.3.2STOP Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21

3.3.3Exit from WAIT Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21

3.4HARDWARE ACTIVATED DIGITAL WATCHDOG FUNCTION . . . . . . . . . . . . . . . . . . . . 22

3.5INTERRUPT . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24

3.5.1Interrupt Vectors/Sources . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24

3.5.2Interrupt Priority . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24

3.5.3Interrupt Option Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25

3.5.4Interrupt Procedure . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25

3.5.5ST638x Interrupt Details . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26

4 ON-CHIP PERIPHERALS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28

4.1I/O PORTS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28

4.1.1Details of I/O Ports . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29

4.1.2I/O Pin Programming . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31

4.1.3Input/Output Configurations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31

4.1.4I/O Port Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31

4.2TIMERS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32

4.2.1Timer Operating Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33

4.2.2Timer Status Control Registers (TSCR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34

4.2.3Timer Counter Registers (TCR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34

4.2.4Timer Prescaler Registers (PSCR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34

4.3SERIAL PERIPHERAL INTERFACE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35

4.3.1S-BUS/I2C BUS Protocol Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35

4.3.2S-BUS/I2C BUS Timing Diagrams . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38

4.3.3Compatibility S-BUS/I2C BUS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40

4.3.4STD SPI Protocol (Shift Register) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41

4.3.5SPI Data/Control Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41

4.414-BIT VOLTAGE SYNTHESIS TUNING PERIPHERAL . . . . . . . . . . . . . . . . . . . . . . . . . . 44

4.4.1Output Details . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44

4.4.2VS Tuning Cell Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44

4.56-BIT PWM D/A CONVERTERS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45

4.6A/D CONVERTER (ADC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46

4.6.1Application Notes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46

4.7DEDICATED LATCHES . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48

4.8ON-SCREEN DISPLAY (OSD) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49

4.8.1Format Specification . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49

4.8.2Format Character Register (FT) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50

4.8.3Application Notes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 57

4.9MIRROR REGISTER . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 58

4.10XOR REGISTER . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 58

5 SOFTWARE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 59

5.1ST6 ARCHITECTURE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 59

5.2ADDRESSING MODES . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 59

5.3INSTRUCTION SET . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 60

6 ELECTRICAL CHARACTERISTICS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 65

6.1ABSOLUTE MAXIMUM RATINGS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 65

6.2RECOMMENDED OPERATING CONDITIONS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 65

6.3DC ELECTRICAL CHARACTERISTICS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 66

6.4AC ELECTRICAL CHARACTERISTICS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 68

7 GENERAL INFORMATION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 69

7.1PACKAGE MECHANICAL DATA . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 69

7.2ORDERING INFORMATION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 69

7.3CUSTOMER EEPROM INITIAL CONTENTS: . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 70

7.4OSD TEST CHARACTER . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 70

7.5ORDERING INFORMATION TABLE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 70

ST63E88,ST63T88, ST63E89,ST63T89 . . . . . . . . . . . . . . . . . .73

1 GENERAL DESCRIPTION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 74

1.1PIN DESCRIPTION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 75

1.2EPROM/OTP DESCRIPTION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 77

1.3EPROM ERASING . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 77

2 ELECTRICAL CHARACTERISTICS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 78

2.1ABSOLUTE MAXIMUM RATINGS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 78

2.2RECOMMENDED OPERATING CONDITIONS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 78

2.3DC ELECTRICAL CHARACTERISTICS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 79

2.4AC ELECTRICAL CHARACTERISTICS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 81

2.5OSD TEST CHARACTER . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 82

ST6380, ST6381, ST6382, ST6383, ST6388, ST6389 1 GENERAL DESCRIPTION

1.1 INTRODUCTION

The ST6380, ST6381, ST6382, ST6383, ST6388, ST6389 microcontrollers are members of the 8-bit HCMOS ST638x family, a series of devices spe-cially oriented to TV applications. Different ROM size and peripheral configurations are available to give the maximum application and cost flexibility. All ST638x members are based on a building block approach: a common core is surrounded by a combination of on-chip peripherals (macrocells) available from a standard library. These peripher-als are designed with the same Core technology providing full compatibility and short design time. Many of these macrocells are specially dedicated to TV applications. The macrocells of the ST638x family are: two Timer peripherals each including an 8-bit counter with a 7-bit software programma-ble prescaler (Timer), a digital hardware activated watchdog function (DHWD), a 14-bit voltage syn-thesis tuning peripheral, a Serial Peripheral Inter-face (SPI), up to six 6-bit PWM D/A converters, up to 7 8-bit A/D Converter, an on-screen display (OSD) with 20 characters per line and 192 charac-ters (in one bank). In addition the following memo-ry resources are available: program ROM (up to 20K), data RAM (256 bytes), EEPROM (384 bytes). Refer to pin configurations figures and to ST638x device summary (Table 1) for the defini-tion of ST638x family members and a summary of differences among the different types.

Table 1. Device Summary

Device

ROM

(Bytes)

RAM

(Bytes)

EEPROM

(Bytes)

ADC VS D/A

Colour

Pins

Emulating Devices

ST63808K 256 384 Yes

Yes

6 3 ST63T88,

ST63E88 ST63818K256 384 Yes

Yes

4 3 ST63T89,

ST63E89 ST638216K 256 384 Yes

Yes

6 3 ST63T88,

ST63E88 ST6383 16K256 384 Yes Yes 4 3 ST63T89, ST63E89 ST638820K256384Yes Yes63ST63T88, ST63E88 ST638920K256384Yes Yes43ST63T89, ST63E89

ST6380, ST6381, ST6382, ST6383, ST6388, ST6389

ST6380, ST6381, ST6382, ST6383, ST6388, ST6389 1.2 PIN DESCRIPTION

V DD and V SS. Power is supplied to the MCU using these two pins. V DD is power and V SS is the ground connection.

OSCin, OSCout. These pins are internally con-nected to the on-chip oscillator circuit. A quartz crystal or a ceramic resonator can be connected between these two pins in order to allow the cor-rect operation of the MCU with various stability/ cost trade-offs. The OSCin pin is the input pin, the OSCout pin is the output pin.

RESET. The active low RESET pin is used to start the microcontroller to the beginning of its program. Additionally the quartz crystal oscillator will be dis-abled when the RESET pin is low to reduce power consumption during reset phase.

TEST. The TEST pin must be held at V SS for nor-mal operation.

PA0-PA7. These 8 lines are organized as one I/O port (A). Each line may be configured as either an input with or without pull-up resistor or as an out-put under software control of the data direction register. Pins PA4 to PA7 are configured as open-drain outputs (12V drive). On PA4-PA7 pins the in-put pull-up option is not available while PA6 and PA7 have additional current driving capability (25mA, V OL:1V). PA0 to PA3 pins are configured as push-pull.

PB0-PB6. These 7 lines are organized as one I/O port (B). Each line may be configured as either an input with or without internal pull-up resistor or as an output under software control of the data direc-tion register. In addition any pin can be configured by software as the input to the Analog to Digital converter. In this case only one pin should be con-figured at any time to avoid conflicts.

PC0-PC7. These 8 lines are organized as one I/O port (C). Each line may be configured as either an input with or without internal pull-up resistor or as an output under software control of the data direc-tion register. Pins PC0 to PC3 are configured as open-drain (5V drive) in output mode while PC4 to PC7 are open-drain with 12V drive and the input pull-up options does not exist on these four pins. PC0, PC1 and PC3 lines when in output mode are “ANDed” with the SPI control signals and are all open-drain. PC0 is connected to the SPI clock sig-nal (SCL), PC1 with the SPI data signal (SDA) while PC3 is connected with SPI enable signal (SEN, used in S-BUS protocol). Pin PC4 and PC6 can also be inputs to software programmable edge sensitive latches which can generate interrupts; PC4 can be connected to Power Interrupt while PC6 can be connected to the IRIN/NMI interrupt line.

DA0-DA5. These pins are the six PWM D/A out-puts of the 6-bit on-chip D/A converters. These lines have open-drain outputs with 12V drive. The output repetition rate is 31.25KHz (with 8MHz clock).

OSDOSCin, OSDOSCout. These are the On Screen Display oscillator terminals. An oscillation capacitor and coil network have to be connected to provide the right signal to the OSD.

HSYNC, VSYNC. These are the horizontal and vertical synchronization pins. The active polarity of these pins to the OSD macrocell can be selected by the user as ROM mask option. If the device is specified to have negative logic inputs, then these signals are low the OSD oscillator stops. If the de-vice is specified to have positive logic inputs, then when these signals are high the OSD oscillator stops. VSYNC is also connected to the VSYNC in-terrupt.

R, G, B, BLANK. Outputs from the OSD. R, G and B are the color outputs while BLANK is the blank-ing output. All outputs are push-pull.

VS. This is the output pin of the on-chip 14-bit volt-age synthesis tuning cell (VS). The tuning signal present at this pin gives an approximate resolution of 40KHz per step over the UHF band. This line is a push-pull output with standard drive.

ST6380, ST6381, ST6382, ST6383, ST6388, ST6389

Figure 2. ST6380, 82, 88 Pin Configuration

Figure 3. ST6381, 83, 89 Pin Configuration

Table 2. Pin Summary

123456789101112131415161718192021

424140393837363534333231302928272625242322

DA0DA1DA2DA3DA4DA5AD1/PB1AD2/PB2AD3/PB3AD4/PB4AD5/PB5AD6/PB6

PA0PA1PA2PA3PA4PA5PA6 (HD0)PA7 (HD1)

V SS

V DD

PC0/SCL PC1/SDA PC2

PC3/SEN PC4/PWRIN PC5

VS OSCin

OSCout TEST/V PP (1)VSYNC BLANK B G R

PC6/IRIN (1) This pin is also the V PP input for OTP/EPROM devices RESET HSYNC OSDOSCout OSDOSCin VR01375

123456789101112131415161718192021

424140393837363534333231302928272625242322

VS DA1DA2DA3DA4AD0/PB0AD1/PB1AD2/PB2AD3/PB3AD4/PB4AD5/PB5AD6/PB6

PA0PA1PA2PA3PA4PA5PA6 (HD0)PA7 (HD1)

V SS

V DD

PC0/SCL PC1/SDA PC2

PC3/SEN PC4/PWRIN PC5

PC7OSCin

OSCout TEST/V PP (1)VSYNC BLANK B G R

PC6/IRIN (1) This pin is also the V PP input for OTP/EPROM devices

RESET HSYNC OSDOSCout OSDOSCin VR01375E

Pin Function Description DA0 to DA5 Output, Open- Drain, 12V

VS Output, Push- Pull R, G, B, BLANK Output, Push- Pull HSYNC, VSYNC Input, Pull- up, Schmitt Trigger OSDOSCin Input, High Impedance OSDOSCout Output, Push- Pull TEST Input, Pull- Down OSCin Input, Resistive Bias, Schmitt Trigger to Reset Logic Only OSCout Output, Push- Pull RESET Input, Pull- up, Schmitt Trigger Input PA0- PA3 I/ O, Push- Pull, Software Input Pull- up, Schmitt Trigger Input 5mA PA4- PA5 I/ O, Open- Drain, 12V, No Input Pull- up, Schmitt Trigger Input PA6- PA7 I/ O, Open- Drain, 12V, No Input Pull- up, Schmitt Trigger Input, High Drive 25mA PB0- PB6 I/ O, Push- Pull/Open Drain, Software Input Pull- up, Schmitt Trigger Input, Analog input PC0- PC3 I/ O, Open- Drain, 5V, Software Input Pull- up, Schmitt Trigger Input 5mA PC4- PC7 I/ O, Open- Drain, 12V, No Input Pull- up, Schmitt Trigger Input 5mA V DD , V SS Power Supply Pins

ST6380, ST6381, ST6382, ST6383, ST6388, ST6389

MEMORY SPACES (Cont’d)

Program ROM Page Register (PRPR)Address: CAh - Write only Reset Value: XXh

D7-D4. These bits are not used but have to be written to “0”.

PRPR3-PRPR0. These are the program ROM banking bits and the value loaded selects the cor-responding page to be addressed in the lower part of 4K program address space as specified in Table 4. This register is undefined on reset.

Caution : This register contains at least one write only bit. Single bit instructions (SET, RES, INC and DEC) should not be used.

Note. Only the lower part of address space has been bankswitched because interrupt vectors and common subroutines should be available all the time. The reason of this structure is due to the fact that it is not possible to jump from a dynamic page to another, unless jumping back to the static page,changing contents of PRPR and then jumping to a different dynamic page.

Care is required when handling the PRPR as it is write only. For this reason, it is not allowed to change the PRPR contents while executing inter-rupts drivers, as the driver cannot save and than restore its previous content. Anyway, this opera-tion may be necessary if the sum of common rou-tines and interrupt drivers will take more than 2K bytes; in this case it could be necessary to divide the interrupt driver in a (minor) part in the static page (start and end), and in the second (major)part in one dynamic page. If it is impossible to avoid the writing of this register in interrupts driv-ers, an image of this register must be saved in a RAM location. Each time the program writes the PRPR register, the image register should also be written. The image register must be written first, so if an interrupt occurs between the two instructions the PRPR is not affected.

Table 3. Program Memory Page Register coding

Table 4. Program Memory Map

----PRPR3PRPR2PRPR1PRPR0

PRPR3PRPR2PRPR1PRPR0PC11Memory Page

X X X X 1

Static Page

(Page 1)

00000Page 0

00010

Page 1 (Static

Page)

00100Page 200110Page 301000Page 401010Page 501100Page 601110Page 710000Page 810010Page 9

Program Memory Page

Device Address Description PAGE 0

0000h-007Fh 0080h-07FFh Reserved User ROM PAGE 1

“STATIC”

0800h-0F9Fh 0FA0h-0FEFh 0FF0h-0FF7h 0FF8h-0FFBh 0FFCh-0FFDh 0FFEh-0FFFh User ROM Reserved Interrupt Vectors

Reserved NMI Vector Reset Vector PAGE 20000h-000Fh 0010h-07FFh Reserved User ROM PAGE 30000h-000Fh 0010h-07FFh Reserved

User ROM (End of 8K ST6380, 81)

PAGE 40000h-000Fh 0010h-07FFh Reserved User ROM PAGE 50000h-000Fh 0010h-07FFh Reserved User ROM PAGE 60000h-000Fh 0010h-07FFh Reserved User ROM PAGE 70000h-000Fh 0010h-07FFh Reserved

User ROM (End of 16K ST6382, 83)

PAGE 80000h-000Fh 0010h-07FFh Reserved User ROM PAGE 9

0000h-000Fh 0010h-07FFh Reserved

User ROM (End of 20K ST6388, 89)

ST6380, ST6381, ST6382, ST6383, ST6388, ST6389

1.3.3 Data Space

The ST6 Core instruction set operates on a specif-ic space, referred to as the Data Space, which contains all the data necessary for the program. Figure 6. Data Space The Data Space allows the addressing of RAM (256 bytes), EEPROM (384 bytes), ST6 Core and peripheral registers, as well as read-only data such as constants and look-up tables.

DATA RAM/EEPROM/OSD

BANK AREA 000h 03Fh

DATA ROM WINDOW AREA 040h 07Fh

X REGISTER080h Y REGISTER081h V REGISTER082h W REGISTER083h

DATA RAM 084h 0BFh

PORT A DATA REGISTER0C0h PORT B DATA REGISTER0C1h PORT C DATA REGISTER0C2h RESERVED0C3h PORT A DIRECTION REGISTER0C4h PORT B DIRECTION REGISTER0C5h PORT C DIRECTION REGISTER0C6h RESERVED0C7h INTERRUPT OPTION REGISTER0C8h DATA ROM WINDOW REGISTER0C9h PROGRAM ROM PAGE REGISTER0CAh RESERVED0CBh SPI DATA REGISTER0CCh PORT B OPTION REGISTER0CDh

RESERVED 0CEh 0CFh

ADC DATA REGISTER0D0h ADC CONTROL REGISTER0D1h TIMER 1 PRESCALER REGISTER0D2h TIMER 1 COUNTER REGISTER0D3h TIMER 1 STATUS/CONTROL REGISTER0D4h

RESERVED 0D5h 0D7h

WATCHDOG REGISTER0D8h

RESERVED0D9h TIMER 2 PRESCALER REGISTER0DAh

TIMER 2 COUNTER REGISTER0DBh TIMER 2 STATUS/CONTROL REGISTER0DCh

RESERVED0DDh MIRROR REGISTER0DEh

XOR REGISTER0DFh DA 0 DATA/CONTROL REGISTER0E0h

DA 1 DATA/CONTROL REGISTER0E1h

DA 2 DATA/CONTROL REGISTER0E2h

DA 3 DATA/CONTROL REGISTER0E3h

IR & VSYNC STATUS REGISTER0E4h

RESERVED0E5h DA 4 DATA/CONTROL REGISTER0E6h

DA 5 DATA/CONTROL REGISTER0E7h DATA RAM BANK REGISTER0E8h DEDICATED LATCHES CONTROL REGISTER0E9h EEPROM CONTROL REGISTER0EAh

SPI CONTROL REGISTER 10EBh

SPI CONTROL REGISTER 20ECh OSD POLARITY SELECT REGISTER0EDh VS DATA REGISTER 10EEh

VS DATA REGISTER 20EFh

RESERVED

0F0h

0F5h

0FEh

ACCUMULATOR0FFh

OSD CONTROL REGISTERS LOCATED IN

PAGE 5 OF BANKED DATA RAM

VERTICAL START ADDRESS REGISTER038h HORIZONTAL START ADDRESS REGISTER039h VERTICAL SPACE REGISTER 003Ah

HORIZONTAL SPACE REGISTER03Bh BACKGROUND COLOUR REGISTER03Ch VERTICAL SPACE REGISTER 103Dh

OSD GLOBAL ENABLE REGISTER03Fh

ST6380, ST6381, ST6382, ST6383, ST6388, ST6389

MEMORY SPACES (Cont’d)

Data ROM Addressing. All the read-only data are physically implemented in the ROM in which the Program Space is also implemented. The ROM therefore contains the program to be executed and also the constants and the look-up tables needed for the program. The locations of Data Space in which the different constants and look-up tables are addressed by the ST6 Core can be considered as being a 64-byte window through which it is pos-sible to access to the read-only data stored in the ROM. This window is located from the 40h ad-dress to the 7Fh address in the Data space and al-lows the direct reading of the bytes from the 000h address to the 03Fh address in the ROM. All the bytes of the ROM can be used to store either in-structions or read-only data. Indeed, the window can be moved by step of 64 bytes along the ROM in writing the appropriate code in the Write-only Data ROM Window register (DRWR, location C9h). The effective address of the byte to be read as a data in the ROM is obtained by the concate-nation of the 6 less significant bits of the address in the Data Space (as less significant bits) and the content of the DRWR (as most significant bits). So when addressing location 40h of data space, and 0 is loaded in the DRWR, the physical addressed location in ROM is 00h.

Note: The data ROM Window can not address window above the 16K byte range.

Data ROM Window Register (DRWR)Address: C9h - Write only Reset Value: XXh

DRWR7-DRWR0. These are the Data Rom Win-dow bits that correspond to the upper bits of data ROM program space. This register is undefined af-ter reset.

Caution : This register contains at least one write only bit. Single bit instructions (SET, RES, INC and DEC) should not be used.

Note: Care is required when handling the DRWR as it is write only. For this reason, it is not allowed to change the DRWR contents while executing in-terrupts drivers, as the driver cannot save and than restore its previous content. If it is impossible to avoid the writing of this register in interrupts drivers, an image of this register must be saved in a RAM location, and each time the program writes the DRWR it writes also the image register. The image register must be written first, so if an inter-rupt occurs between the two instructions the DRWR register is not affected.

Figure 7. Data ROM Window Memory Addressing

DRWR 7DRWR 6DRWR 5DRWR 4DRWR 3DRWR 2DRWR 1DRWR 0

DATA ROM

WINDOW REGISTER CONTENTS

DATA SPACE ADDRESS

40h-7Fh

IN INSTRUCTION

PROGRAM SPACE ADDRESS

678910110

VR01573B

121

0DATA SPACE ADDRESS

59h

Example:

(DWR)

DWR=28h

11000000001ROM

ADDRESS:A19h

ST6380, ST6381, ST6382, ST6383, ST6388, ST6389 MEMORY SPACES (Cont’d)

1.3.4 Data RAM/EEPROM/OSD RAM Addressing

In all members of the ST638x family 64 bytes of data RAM are directly addressable in the data space from 80h to BFh addresses. The additional 192 bytes of RAM, the 384 bytes of EEPROM, and the OSD RAM can be addressed using the banks of 64 bytes located between addresses 00h and 3Fh. The selection of the bank is done by pro-gramming the Data RAM Bank Register (DRBR) located at the E8h address of the Data Space. In this way each bank of RAM, EEPROM or OSD RAM can select 64 bytes at a time. No more than one bank should be set at a time.

Data RAM Bank Register (DRBR)

Address: E8h - Write only

Reset Value: XXh

DRBR7,DRBR1,DRBR0. These bits select the EEPROM pages.

DRBR6, DRBR5. Each of these bits, when set, will select one OSD RAM register page.

DRBR4,DRBR3,DRBR2. Each of these bits, when set, will select one RAM page.

This register is undefined after reset.

Table 5 summarizes how to set the Data RAM Bank Register in order to select the various banks or pages.Caution: This register contains at least one write only bit. Single bit instructions (SET, RES, INC and DEC) should not be used.

Note: Care is required when handling the DRBR as it is write only. For this reason, it is not allowed to change the DRBR contents while executing in-terrupts drivers, as the driver cannot save and than restore its previous content. If it is impossible to avoid the writing of this register in interrupts drivers, an image of this register must be saved in a RAM location, and each time the program writes the DRBR it writes also the image register. The im-age register must be written first, so if an interrupt occurs between the two instructions the DRBR is not affected.

Table 5. Data RAM Bank Register Set-up

DRBR

7DRBR

DRBR

DRBR Value

Selection

Hex.Binary

01h0000 0001EEPROM Page 0

02h0000 0010EEPROM Page 1

03h0000 0011EEPROM Page 2

81h1000 0001EEPROM Page 3

82h1000 0010EEPROM Page 4

83h1000 0011EEPROM Page 5

04h0000 0100RAM Page 2

08h0000 1000RAM Page 3

10h0001 0000RAM Page 4

20h0010 0000OSD Page 5

ST6380, ST6381, ST6382, ST6383, ST6388, ST6389 MEMORY SPACES (Cont’d)

EEPROM Description

The data space of ST638x family from 00h to 3Fh is paged as described in Table 5. 384 bytes of EEPROM located in six pages of 64 bytes (pages 0,1,2,3,4 and 5, see Table 5).

Through the programming of the Data RAM Bank Register (DRBR=E8h) the user can select the bank or page leaving unaffected the way to ad-dress the static registers. The way to address the “dynamic” page is to set the DRBR as described in Table 5 (e.g. to select EEPROM page 0, the DRBR has to be loaded with content 01h, see Data RAM/EEPROM/OSD RAM addressing for additional information). Bits 0, 1 and 7 of the DRBR are dedicated to the EEPROM.

The EEPROM pages do not require dedicated in-structions to be accessed in reading or writing. The EEPROM is controlled by the EEPROM Con-trol Register (EECR=EAh). Any EEPROM location can be read just like any other data location, also in terms of access time.

To write an EEPROM location takes an average time of 5 ms (10ms max) and during this time the EEPROM is not accessible by the Core. A busy flag can be read by the Core to know the EEPROM status before trying any access. In writing the EEPROM can work in two modes: Byte Mode (BMODE) and Parallel Mode (PMODE). The BMODE is the normal way to use the EEPROM and consists in accessing one byte at a time. The PMODE consists in accessing 8 bytes per time. EEPROM Control Register (EECR)

Address: EAh - Read only/Write only

Reset Value:

D7. Not used

Caution: This register contains at least one write only bit. Single bit instructions (SET, RES, INC and DEC) should not be used.

SB. WRITE ONLY. If this bit is set the EEPROM is disabled (any access will be meaningless) and the power consumption of the EEPROM is reduced to the leakage values.

D5, D4. Reserved for testing purposes, they must be set to zero.

PS. WRITE ONLY. Once in Parallel Mode, as soon as the user software sets the PS bit the par-allel writing of the 8 adjacent registers will start. PS is internally reset at the end of the programming procedure. Note that less than 8 bytes can be writ-ten; after parallel programming the remaining un-defined bytes will have no particular content. PE. WRITE ONLY. This bit must be set by the user program in order to perform parallel programming (more bytes per time). If PE is set and the “parallel start bit” (PS) is low, up to 8 adjacent bytes can be written at the maximum speed, the content being stored in volatile registers. These 8 adjacent bytes can be considered as row, whose A7, A6, A5, A4, A3 are fixed while A2, A1 and A0 are the changing bytes. PE is automatically reset at the end of any parallel programming procedure. PE can be reset by the user software before starting the program-ming procedure, leaving unchanged the EEPROM registers.

BS. READ ONLY. This bit will be automatically set by the CORE when the user program modifies an EEPROM register. The user program has to test it before any read or write EEPROM operation; any attempt to access the EEPROM while “busy bit” is set will be aborted and the writing procedure in progress completed.

EN. WRITE ONLY. This bit MUST be set to one in order to write any EEPROM register. If the user program will attempt to write the EEPROM when EN= “0” the involved registers will be unaffected and the “busy bit” will not be set.

After RESET the content of EECR register will be 00h.

Notes: When the EEPROM is busy (BS=”1”) the EECR can not be accessed in write mode, it is only possible to read BS status. This implies that as long as the EEPROM is busy it is not possible to change the status of the EEPROM control register. EECR bits 4 and 5 are reserved for test purposes, and must never be set to “1”.

70 -SB--PS PE BS EN

ST6380, ST6381, ST6382, ST6383, ST6388, ST6389 MEMORY SPACES (Cont’d)

Additional Notes on Parallel Mode. If the user wants to perform a parallel programming the first action should be the setting of the PE bit; from this moment, the first time the EEPROM will be ad-dressed in writing, the ROW address will be latched and it will be possible to change it only at the end of the programming procedure or by reset-ting PE without programming the EEPROM. After the ROW address latching the Core can “see” just one EEPROM row (the selected one) and any attempt to write or read other rows will produce errors. Do not read the EEPROM while PE is set.

As soon as PE bit is set, the 8 volatile ROW latch-es are cleared. From this moment the user can load data in the whole ROW or just in a subset. PS setting will modify the EEPROM registers corre-sponding to the ROW latches accessed after PE.For example, if the software sets PE and accesses EEPROM in writing at addresses 18h,1Ah,1Bh and then sets PS, these three registers will be modified at the same time; the remaining bytes will have no particular content. Note that PE is inter-nally reset at the end of the programming proce-dure. This implies that the user must set PE bit be-tween two parallel programming procedures. Any-way the user can set and then reset PE without performing any EEPROM programming. PS is a set only bit and is internally reset at the end of the programming procedure. Note that if the user tries to set PS while PE is not set there will not be any programming procedure and the PS bit will be un-affected. Consequently PS bit can not be set if EN is low. PS can be affected by the user set if, and only if, EN and PE bits are also set to one.

ST6380, ST6381, ST6382, ST6383, ST6388, ST6389

3 CLOCKS, RESET, INTERRUPTS AND POWER SAVING MODES 3.1 ON-CHIP CLOCK OSCILLATOR

The internal oscillator circuit is designed to require a minimum of external components. A crystal quartz, a ceramic resonator, or an external signal (provided to the OSCin pin) may be used to gener-ate a system clock with various stability/cost trade-offs. The typical clock frequency is 8MHz. Please note that different frequencies will affect the oper-ation of those peripherals (D/As, SPI) whose refer-ence frequencies are derived from the system clock.

The different clock generator connection schemes are shown in Figure 10 and 11. One machine cycle takes 13 oscillator pulses; 12 clock pulses are needed to increment the PC while and additional 13th pulse is needed to stabilize the internal latch-es during memory addressing. This means that with a clock frequency of 8MHz the machine cycle is 1.625μSec.

The crystal oscillator start-up time is a function of many variables: crystal parameters (especially RS), oscillator load capacitance (CL), IC parame-ters, ambient temperature, and supply voltage.It must be observed that the crystal or ceramic leads and circuit connections must be as short as possi-ble. Typical values for CL1 and CL2 are in the range of 15pF to 22pF but these should be chosen based on the crystal manufacturers specification. Typical input capacitance for OSCin and OSCout pins is 5pF.

The oscillator output frequency is internally divided by 13 to produce the machine cycle and by 12 to produce the Timers and the Watchdog clock. A byte cycle is the smallest unit needed to execute any operation (i.e., increment the program coun-ter). An instruction may need two, four, or five byte cycles to be executed (See Table 6).

Table 6. Instruction Timing with 8MHz Clock Figure 10. Clock Generator Option 1 Figure 11. Clock Generator Option 2 Figure 12. OSCin, OSCout Diagram

Instruction Type Cycles Execution Time

Branch if set/reset 5 Cycles8.125μs Branch & Subroutine Branch 4 Cycles 6.50μs Bit Manipulation 4 Cycles 6.50μs Load Instruction 4 Cycles 6.50μs Arithmetic & Logic 4 Cycles 6.50μs Conditional Branch 2 Cycles 3.25μs Program Control 2 Cycles 3.25μs

OSC in OSC out

C L1C

ST6xxx

CRYSTAL/RESONATOR CLOCK

VA0016B

OSC in OSC out

ST6xxx

EXTERNAL CLOCK

VA0015C

VA00462

OSCout In

OSCin, OSCout (QUARTZ PINS)

OSCin

1M V

ST6380, ST6381, ST6382, ST6383, ST6388, ST6389 3.2 RESETS

The MCU can be reset in three ways:

– by the external Reset input being pulled low;

– by Power-on Reset;

– by the digital Watchdog peripheral timing out.

3.2.1 RESET Input

The RESET pin may be connected to a device of the application board in order to reset the MCU if required. The RESET pin may be pulled low in RUN, WAIT or STOP mode. This input can be used to reset the MCU internal state and ensure a correct start-up procedure. The pin is active low and features a Schmitt trigger input. The internal Reset signal is generated by adding a delay to the external signal. Therefore even short pulses on the RESET pin are acceptable, provided V DD has completed its rising phase and that the oscillator is running correctly (normal RUN or WAIT modes). The MCU is kept in the Reset state as long as the RESET pin is held low.

If RESET activation occurs in RUN or WAIT modes, processing of the user program is stopped (RUN mode only), the Inputs and Outputs are con-figured as inputs with pull-up resistors if available. When the level on the RESET pin then goes high, the initialization sequence is executed following expiry of the internal delay period.

If RESET pin activation occurs in the STOP mode, the oscillator starts up and all Inputs and Outputs are configured as inputs with pull-up resistors if available. When the level of the RESET pin then goes high, the initialization sequence is executed following expiry of the internal delay period.

3.2.2 Power-on Reset

The function of the POR circuit consists in waking up the MCU at an appropriate stage during the power-on sequence. At the beginning of this se-quence, the MCU is configured in the Reset state: all I/O ports are configured as inputs with pull-up resistors and no instruction is executed. When the power supply voltage rises to a sufficient level, the oscillator starts to operate, whereupon an internal delay is initiated, in order to allow the oscillator to fully stabilize before executing the first instruction. The initialization sequence is executed immediate-ly following the internal delay.

The internal delay is generated by an on-chip counter. The internal reset line is released 2048 in-ternal clock cycles after release of the external re-set.

The internal POR device is a static mechanism which forces the reset state when V DD is below a threshold voltage in the range 3.4 to 4.2 Volts (see Figure 13). The circuit guarantees that the MCU will exit or enter the reset state correctly, without spurious effects, ensuring, for example, that EEP-ROM contents are not corrupted.

Figure 13. Power ON/OFF Reset operation Figure 14. Reset and Interrupt Processing

VR02037

V DD

4.2

3.4

t POWER

ON/OFF

Threshold

RESET

INT LATCH CLEARED

NMI MASK SET

RESET

( IF PRESENT )

SELECT

NMI MODE FLAGS

IS RESET STILL

PRESENT?

YES

PUT FFEH

ON ADDRESS BUS

FROM RESET LOCATIONS

FFE/FFF

FETCH INSTRUCTION

LOAD PC

VA000427

ST6380, ST6381, ST6382, ST6383, ST6388, ST6389