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A3992-Datasheet

Description

Designed for pulse width modulated (PWM) current control of bipolar microstepped stepper motors, the A3992 is capable of continuous output currents to ±1.5 A and operating voltages to 50 V . Internal fixed off-time PWM current control timing circuitry can be programmed via the serial interface to operate in slow, fast, or mixed decay modes.

The desired load current level is set via the serial port with two six bit linear DACs in conjunction with a reference voltage. The six bits of control allow maximum flexibility in torque control for a variety of step methods, from microstepping to full step drive. Load current is set in 1.56% increments of the maximum value.Synchronous rectification circuitry allows the load current to flow through the low R DS(on) of the DMOS output driver during current decay. This feature eliminates the need for external clamp diodes in most applications, saving cost and external component count, while minimizing power dissipation.

Internal circuit protection includes short-to-ground, shorted load, thermal shutdown with hysteresis, and crossover current protection. Special power up sequencing is not required.

The A3992 is supplied in a thin profile (1.2 mm maximum height) 24 pin TSSOP (suffix LP) with exposed thermal pad and a 24 pin plastic DIP with dual copper batwing tabs (suffix B). The exposed thermal pad on the LP is at ground potential and needs no electrical isolation. Both packages are lead (Pb) free with 100% matte tin leadframe plating.

Features and Benefits

? ±1.5 A, 50 V continuous output rating ? Low R DS(on) DMOS output drivers ? Short-to-ground protection ? Shorted load protection

? Optimized microstepping via six bit linear DACs

? Programmable mixed, fast, and slow current decay modes ? 4 MHz internal oscillator for digital timing ? Serial interface controls chip functions

? Synchronous rectification for low power dissipation ? Internal UVLO and thermal shutdown circuitry ? Crossover-current protection

? Inputs compatible with 5 or 3.3 V control signals ? Sleep and Idle modes

DMOS Dual Full-Bridge Microstepping PWM Motor Driver

Packages

Typical Application

LP package approximate scale

24 pin batwing DIP (suf ? x B) and 24 pin TSSOP with

exposed thermal pad (suf ?

x LP)

T hermal Characteristics*Characteristic

Symbol

Notes

Rating Units Package Thermal Resistance

R θJA

B package on 4-layer PCB

26°C/W B package on 2-layer PCB with 3.15 in.2

2 oz. copper each side 36°C/W LP package on 4-layer PCB

28°C/W LP package on 2-layer PCB with 3.8 in.2 2 oz. copper each side

°C/W

*Additional thermal data available on the Allegro website.

Selection Guide

Part Number Packing

Package

A3992SB-T 15 pieces/tube 24 pin batwing DIP A3992SLPTR-T

Tape, 4000 pieces/reel

24 pin TSSOP with exposed thermal pad

Absolute Maximum Ratings

Characteristic

Symbol Notes

Rating Units Load Supply Voltage V BB 50V Output Current I OUT Output current rating may be limited by duty cycle, ambient temperature, and heat sinking. Under any set of conditions, do not exceed the speci ? ed current rating or a junction tempera-ture of 150°C.

±1.5A Logic Supply Voltage V DD 7.0V Logic Input Voltage Range V IN

–0.3 to 7

V VBBx to OUTx Voltage 50V OUTx to SENSEx Voltage 50V REF Reference Voltage V REF 3V SENSE Voltage (DC)

V SENSE 500mV Operating Ambient Temperature T A Range S

–20 to 85oC Maximum Junction Temperature T J (max)150oC Storage Temperature

T stg

–55 to 150

Functional Block Diagram

ELECTRICAL CHARACTERISTICS1 valid at T A= 25°C, V BB = 50 V, f PWM < 50 kHz, unless otherwise noted

Characteristic Symbol Test Conditions Min.Typ.2Max.Units Output Drivers

Load Supply Voltage Range V BB Operating, I OUT = ±1.5 A15–50V During Sleep mode0–50V

Output Leakage Current I DSS V OUT = V BB–<1.050μA V OUT = 0 V–<–1.0–50μA

Output On Resistance R DS(on)Source driver, I OUT = -1.5 A–0.540.6ΩSink driver, I OUT = 1.5 A–0.540.6Ω

Body Diode Forward Voltage V F Source diode, I F = -1.5 A–– 1.2V Sink diode, I F = 1.5 A–– 1.2V

Motor Supply Current I BB f PWM < 50 kHz ––8mA Operating, outputs disabled––6mA Sleep or Idle mode––20μA

Logic Supply Current I DD f PWM < 50 kHz––12mA Outputs off––10mA Idle mode (Word 1, D18 = 0) –– 1.5mA Sleep mode ––100μA

Control Logic

Logic Supply Voltage Range V DD Operating 4.55 5.5V

Logic Input Voltage V IN(1) 2.0––V V IN(0)––0.8V

Logic Input Current I IN(1)V IN = 2.0 V–<1.020μA I IN(0)V IN = 0.8 V–<–2.0–20μA

Input Hysteresis0.20–0.40V Minimum sleep pulse width t S> 2––μs OSC input frequency f OSC(in)Divide by 1 (Word 2, D13=0, D14=1) 2.5–6MHz OSC input duty cycle40–60%

Internal Oscillator f OSC OSC shorted to GND345MHz R OSC= 51 kΩ 3.44 4.6MHz

DAC Accuracy V DAC Measured relative to REF buffer output–±0.5–LSB Reference Input Voltage Range.5– 2.6V Reference Buffer Offset V OS–±10–mV

Reference Divider Ratio V REF/V SENSE Word 0, D18 = 0, D17 = 1, V REF = 0.5 to 2.6 V7.488.8–Word 0, D18 = 1, D17 = 1, V REF =0.5 to 2.6 V 3.64 4.4–

Reference Input Current I REF V REF = 2.0 V–0.5–0.5μA Internal Reference Voltage V REFINT 1.940 2.0 2.060V Comparator Input Offset Volt.V IO V REF = 0 V–505mV

G M Error3V ERR Internal V REF, Range = 8, DAC = 63–606% Internal V REF, Range = 8, DAC = 31–909% Internal V REF, Range = 4, DAC = 63–606% Internal V REF, Range = 4, DAC = 15–10010%

Propagation Delay Times t pd 50% to 90%; PWM change to source on5008001000ns 50% to 90%; PWM change to source off35–250ns 50% to 90%; PWM change to sink on5008001000ns 50% to 90%; PWM change to sink off35–250ns

Crossover Dead Time t DT300650900ns UVLO Enable Threshold V UVLO V DD rising 3.9 4.2 4.45V UVLO Hysteresis V UVLOHYS0.050.10–V Protection Circuitry

Overcurrent Protection Threshold4I OCPST2––A Overcurrent Blanking t OCP1–3μs Thermal Shutdown Temperature T J–165–°C Thermal Shutdown Hysteresis T JHYS–15–°C 1Negative current is de? ned as coming out of (sourcing) the speci? ed device pin.

2Typical data are for initial design estimations only, and assume optimum manufacturing and application conditions. Performance may vary for individual units, within the speci? ed maximum and minimum limits.

3V ERR = [(V REF / Range) – V SENSE ]/ (V REF / Range).

4OCP is tested at T A = 25°C in a restricted range and guaranteed by characterization.

The A3992 is controlled via a 3 wire serial port. The programmable functions allow maximum ? exibility in con? guring the PWM to the motor drive requirements. The serial data is written as two 19 bit words, 1 bit

to select which word (referred to here as Word 0 and Word 1) and 18 bits of data. The serial port is de? ned in the following tables and text descriptions.

Word 0 Bit Assignments

Word 0 is selected by setting D0 = 0. Assignments are summarized in the following table, and described in detail in the remainder of this section.

Word 0 Bit Assignments

Bit Function

D0Word Select = 0

D1Bridge 1, DAC, LSB

D2Bridge 1, DAC, Bit2

D3Bridge 1, DAC, Bit3

D4Bridge 1, DAC, Bit4

D5Bridge 1, DAC, Bit 5

D6Bridge 1, DAC, MSB

D7Bridge 2, DAC, LSB

D8Bridge 2, DAC, Bit2

D9Bridge 2, DAC, Bit3

D10Bridge 2, DAC, Bit4

D11Bridge 2, DAC, Bit 5

D12Bridge 2, DAC, MSB

D13Bridge 1 Phase

D14Bridge 2 Phase

D15Bridge 1 Mode

D16Bridge 2 Mode

D17Reference Select

D18Range Select

D1 – D6 Bridge 1, Linear DAC. 6 bit word to set de-sired current level for bridge 1. Setting all bits to zero disables Full Bridge 1, all drivers off. (See Current Regulation in the Functional Description section.)D7 – 12 Bridge 2 Linear DAC. 6 bit word to set the desired current level for bridge 2. Setting all bits to zero disables Full Bridge 2, all drivers off. (See Cur-rent Regulation in the Functional Description section.) D13 Bridge 1 Phase. This bit controls the direction of current for motor phase 1 as de? ned below:

D13OUT1A OUT1B

0L H

1H L

D14 Bridge 2 Phase. This bit controls the direction of current for motor phase 2 as de? ned below:

D14OUT2A OUT2B

0L H

1H L

D15 Bridge 1 Mode. This bit determines the decay for Full Bridge 1 as de? ned below:

D15Mode

0Mixed Decay

1Slow Decay

D16 Bridge 2 Mode. This bit determines the decay for Full Bridge 2 as de? ned below:

D16Mode

0Mixed Decay

1Slow Decay

D17 Ref Select. This bit determines the reference input for the two 6 bit linear DACs. Logic low selects internal 2 V reference voltage, logic high selects ex-ternal reference input on the REF pin.

D18 G m Range Select. D18 determines if the scaling factor used is 4 or 8:

D18Divider Load Current

0÷8I TRIP = V DAC/(R SENSE × 8)

1÷4I TRIP = V DAC/(R SENSE × 4)

Serial Interface Description

Word 1 Bit Assignments

Word 1 is selected by setting D0 = 1. Assignments are summarized in the following table, and described in detail in the remainder of this section.

Word 1 Bit Assignments

Bit Function

D0Word Select = 1

D1 Blank

Time

LSB

D2Blank Time MSB

D3Off Time LSB

D4Off Time Bit1

D5Off Time Bit2

D6Off Time Bit3

D7Off Time MSB

D8Fast Decay Time LSB

D9Fast Decay Time Bit1

D10Fast Decay Time Bit2

D11Fast Decay Time MSB

D12C0 Oscillator Control

D13C1 Oscillator Control

D14SR Control Bit 1

D15SR Control Bit 2

D16Reserved for testing

D17 Reserved for testing

D18Idle Mode

D1 – D2 Blank Time. 2 bits to set the blank time scal-ing factor for the current sense comparator:

D2D1Time

00 4 × P OSC

01 6 × P OSC

108 × P OSC

1112 × P OSC

When a source driver turns on, a current spike occurs due to the reverse recovery currents of the clamp di-odes and/or switching transients related to distributed capacitance in the load. To prevent this current spike from erroneously resetting the source enable latch, the sense comparator is blanked. The blank timer runs after the off time counter to provide the programmable blanking function. The blank timer is reset when PHASE is changed.

D3 – D7 Fixed Off Time. 5 bits to set the ? xed

off-time for the internal PWM control circuitry. Fixed off-time is de? ned by:

t OFF = (1 + n) × P OSC × 8 – P OSC ,

where n = 0 to 31.

For example, with a master oscillator frequency of

4 MHz ( P OSC = 250 ns), the ? xed off-time is adjust-able from 1.7

5 to 63.75 μs, in increments of 2 μs.

D8 – D11 Fast Decay Time. 4 bits to set the fast decay portion of ? xed off-time for the internal PWM control circuitry. The fast decay portion is de? ned by: t fd = (1 + n) × P OSC × 8 – P OSC ,

where n = 0 to 15.

For example, with a master oscillator frequency of

4 MHz ( P OSC = 250 ns), the ? xed off-time is adjust-able from 1.7

5 to 31.75 μs, in increments of 2 μs. For t fd > t off , the device will effectively operate in fast decay mode.

D12 – D13 Oscillator Control. 2 bits to set timing options:

D13 D12Source and Rate

00Internal clock 4 MHz

01External clock f ÷ 1

10External clock f ÷ 2

11External clock f ÷ 4

A 4 MHz internal oscillator can be used for the tim-ing functions. If more precise control is required, an external oscillator can be input to OSC pin. To accom-modate a wider range of system clocks, an internal divider is provided to generate the desired MO fre-quency.

VREG.The VREG pin should be decoupled with a 0.22 F capacitor to ground. This internally gener-ated supply voltage is used to run the sink side DMOS outputs. VREG is internally monitored and in the case of a fault condition, the outputs of the device are disabled.

Current Regulation. The reference voltage can be set by analog input to the REF terminal, or via the internal 2 V precision reference. The choice of reference volt-age and selection of sense resistor set maximum trip current, as follows:

I TRIPMAX = V REF / (Range × R SENSE) . Microstepping current levels are set according to the following equations:

I TRIP = V DAC / (Range × R SENSE) , and

V DAC = ((1+DAC) × V REF) / 64 ,

where DAC is the input code, 1 to 63 (Word 0, D1 to

D12), and Range is 4 or 8, as selected by Word 0, D18. Programming a DAC input code to 0 disables the cor-responding bridge, and results in minimum load current. PWM Timer Function. The PWM timer is program-mable via the serial port to provide ? xed off-time PWM signals to the control block. In mixed decay mode, the ? rst portion of the off-time operates in fast decay, until the fast decay time count is reached, fol-lowed by slow decay for the remainder of the ? xed

off-time. If the fast decay time is set longer than the off-time, the device effectively operates in fast decay mode. Oscillator. The PWM timer is based on an oscillator input, typically 4 MHz. The A3992 can be con? gured to select either the 4 MHz internal oscillator or, if more precise accuracy is required, an external clock can be connected to the OSC terminal. If an external clock is used, 3 internal divider choices are selectable via the serial port to allow ? exibility in choosing f OSC based on available system clocks. If the internal oscil-lator option is used, the absolute accuracy is dependent on process variation of resistance and capacitance.

A precision resistor can be connected from the OSC terminal to V DD to further improve the tolerance. The frequency is calculated as:

f OSC = 204 × 109 / R OSC .

If the internal oscillator is used without the external re-sistor the OSC terminal should be connected to GND.

D14 – D15 Synchronous Recti? cation. 2 bits set the different modes of operation (see Synchronous Recti? -cation in the Functional Description section):

D15D14Synchronous Rectifier

00Active

01Disabled

10Passive

11Allegro defined use D16, D17 (Reserved). 2 bits reserved for testing. They should be programmed to 0 during normal op-eration.

D18 Idle Mode. The device can be put into the low-power Idle mode by writing a 0 to D18. The outputs are disabled, the charge pump turned off, and the de-vice consumes a lower supply current. The undervolt-age monitor circuit remains active.

Functional Description

Charge Pump (CP1 and CP2). The charge pump is

used to generate a gate supply greater than V BB x to drive the source FET gates. A 0.22 μF ceramic capaci-tor is required between CP1 and CP2 for pumping purposes. A 0.22 μF ceramic capacitor is required between VCP and the VBB terminals to act as a reser-voir to operate the high-side FETs.

Sleep Mode. Control input on the SLEEP pin is used

to minimize power consumption when not the device is not in use. This disables much of the internal circuit-ry including the output DMOS, regulator, and charge pump. Logic low puts the device into Sleep mode, logic high allows normal operation and startup of the device into the home position. When asserted low, the serial port is reset. All bits are reset to 0s, with the exception of D7, the ? xed off-time MSB, which is set to 1. This prevents the off-time from being too short, which could result in a loss of current control. When coming out of Sleep mode, allow 1 ms before issuing a step command, to allow the charge pump to stabilize.

Shutdown. In the event of a fault due to excessive

junction temperature, or to low voltage on V CP or V REG , the outputs of the device are disabled until the fault condition is removed. At power up, and in the event of low V DD , the UVLO circuit disables the driv-ers and resets the data in the serial port.

Short to Ground. Should a motor winding short to

ground, the current through the short will rise until the overcurrent (OCP) threshold is exceeded, a minimum of 2 A. The driver will turn off after a short propaga-tion delay and latch the device. The device will remain latched until the SLEEP input goes high or VDD power is removed. As shown in panel A of the ? gure below, a short to ground will produce a single overcur-rent event.

Shorted Load. During a shorted load event, the cur-

rent path is through the sense resistor. The device will be protected, however, the device does not see this as a fault because the current path is not interrupted, so this condition will not latch the part.

When a bridge turns on, the current will rise and ex-ceed the overcurrent threshold. After a blank time of approximately 1μs, the driver will look at the voltage on the SENSE pin. The voltage on the SENSE pin will be larger than the voltage set by the VREF pin, and the bridge will turn off for the time set by the OSC pin. Panel B of the ? gure below shows a shorted load condition with an off-time of 30 μs.

MUX. The MUX pin is reserved for Allegro internal use and has no function to the end user. In the applica-tion, this pin can be tied to ground or left ? oating.

(A) Short-to-ground event

(B) Short-to-load event

t off = 30 μs

2 A / div.5 μs / div.2 A / div.

500 ns / div.Fault latched

Current Sensing. To minimize inaccuracies in sens-ing the I PEAK current level caused by ground trace I ?R

drops, the sense resistor should have an independent ground return to the GND terminal of the device. For low value sense resistors, the I ?R drops in the PCB sense resistor traces can be signi ? cant and should be taken into account. The use of sockets should be avoided because they can introduce variation in R SENSE due to their contact resistance.

Allegro MicroSystems recommends a value of R SENSE given by:

R SENSE = 0.5 / I TRIP MAX .

Thermal Protection . Circuitry turns off all drivers

when the junction temperature reaches 165°C typical. It is intended only to protect the device from failures due to excessive junction temperatures, and should not imply that output short circuits are permitted. Thermal shutdown has a hysteresis of approximately 15°C.

Serial Port Write Timing Operation. Data is clocked

into a shift register on the rising edge of a CLOCK signal. Normally, STROBE is held high, and is only brought low to initiate a write cycle. The data is writ-ten MSB ? rst. Refer to the diagram below for timing requirements.

Synchronous Recti ? cation. When a PWM off-cycle

is triggered, by a bridge disable command or internal

? xed off-time cycle, load current recirculates accord-ing to the decay mode selected by control logic. The

A3992 synchronous recti ? cation feature turns on the

appropriate MOSFETs during current decay, and effec-tively shorts out the body diodes with the low R DS(on)

driver. This lowers power dissipation signi ? cantly, and can eliminate the need for external Schottky diodes for most applications.Three distinct modes of operation can be con ? gured

with the two serial port control bits:

1. Active mode . Prevents reversal of load current. Turns off synchronous recti ? cation when a 0 current level is detected.

2. Passive mode . Allows reversal of current, but will

turn off the synchronous recti ? er circuit if the load

current inversion ramps up to the current limit.

3. Disabled . Prevents MOSFET switching during load

recirculation in fast decay portion of the off-time. Dur-ing the slow decay portion of the off-time, the low-side switch turns on, which recirculates current through the

low-side MOSFET and low-side body diode.Applications Notes

DATA

CLOCK

STROBE SLEEP

A. Minimum Data Setup Time 15 ns

B. Minimum Data Hold Time

10 ns C. Minimum Setup Strobe to Clock rising edge 120 ns D. Minimum Clock High Pulse Width 40 ns E. Minimum Clock Low Pulse Width

40 ns

F. Minimum Setup Clock rising edge to Strobe 50 ns G . Minimum Strobe Pulse Width

120 ns H. Minimum Sleep to Clock Setup Time 50 μs I. Setup “Idle” Release to Output Enable

1 ms

Serial Port Timing Diagram

Layout. The printed circuit board should use a heavy groundplane. For optimum electrical and thermal performance, the A3992 must be soldered directly onto the board. On the underside of the A3992 pack-age is an exposed pad, which provides a path for enhanced thermal dissipation. The thermal pad should be soldered directly to an exposed surface on the PCB. Thermal vias are used to transfer heat to other layers of the PCB.

In order to minimize the effects of ground bounce and offset issues, it is important to have a low impedance single-point ground, known as a star ground, located very close to the device. By making the connection be-tween the pad and the ground plane directly under the A3992, that area becomes an ideal location for a star ground point. A low impedance ground will prevent ground bounce during high current operation and en-sure that the supply voltage remains stable at the input terminal. The recommended PCB layout, shown in the diagram below, illustrates how to create a star ground under the device, to serve both as a low impedance ground point and thermal path.

The two input capacitors should be placed in parallel, and as close to the device supply pins as possible. The ceramic capacitor (CVBB1) should be closer to the pins than the bulk capacitor (CVBB2). This is neces-sary because the ceramic capacitor will be responsible for delivering the high frequency current components. The sense resistors, RSx , should have a very low impedance path to ground, because they must carry

a large current while supporting very accurate volt-age measurements by the current sense comparators. Long ground traces will cause additional voltage drops, adversely affecting the ability of the compara-tors to accurately measure the current in the wind-ings. As shown in the layout below, the SENSEx pins have very short traces to the RSx resistors and very thick, low impedance traces directly to the star ground underneath the device.

LP package layout shown

Terminal List Table

Number Name

Pin Description

B Package LP Package

119VCP Reservoir capacitor terminal 220CP1Charge pump capacitor terminal 321CP2Charge pump capacitor terminal 422OUT1B DMOS Full Bridge 1, output B 524VBB1Load supply

6, 7, 18, 19

7, 18GND Ground. On B package, internally fused to the die pad for enhanced thermal dissipation.81SENSE1Sense resistor terminal for Full Bridge 192OUT1A DMOS Full Bridge 1, output A 104STROBE Logic input 115CLOCK Logic input 126DATA Logic input 138REF G m reference input 149MUX Not used 1510VDD Logic supply

1611OUT2A DMOS Full Bridge 2, output A

1712SENSE2Sense resistor terminal for Full Bridge 22013VBB2Load supply

2114OUT2B DMOS Full Bridge 2, output B 2215VREG Internal regulator 2316SLEEP Logic input 2417OSC Oscillator input –3, 23NC No connection

–

PAD

Exposed thermal pad for enhanced thermal dissipation.

123456789101112

242322212019181716151413OSC SLEEP VREG OUT2B VBB2GND GND SENSE2OUT2A VDD MUX REF

VCP CP1CP2OUT1B VBB1GND GND SENSE1OUT1A STROBE CLOCK DATA B Package

3456789101112

242322212019181716151413VBB1NC OUT1B CP2CP1VCP GND OSC SLEEP VREG OUT2B VBB2

SENSE1OUT1A NC STROBE CLOCK DATA GND REF MUX VDD OUT2A SENSE2PAD

LP Package

Device Pin-out Diagrams

Dimensions exclusive of mold flash, gate burrs, and dambar protrusions Exact case and lead configuration at supplier discretion within limits shown A For Reference Only

(reference JEDEC MS-001 BE)Dimensions in millimeters

+0.76–0.25

+0.51–0.38

10.92+0.251.52+0.10–0.05

Package LP

, 24 Pin TSSOP with Exposed Thermal Pad

A Terminal #1 mark area

For Reference Only

(reference JEDEC MO-153 ADT)

Dimensions in millimeters

Dimensions exclusive of mold flash, gate burrs, and dambar protrusions

Exact case and lead configuration at supplier discretion within limits shown

Reference land pattern layout (reference IPC7351

TSOP65P640X120-25M); all pads a minimum of 0.20 mm from all

adjacent pads; adjust as necessary to meet application process

requirements and PCB layout tolerances; when mounting on a multilayer

PCB, thermal vias at the exposed thermal pad land can improve thermal

dissipation (reference EIA/JEDEC Standard JESD51-5)

PCB Layout Reference View

Exposed thermal pad (bottom surface)

+0.05

–0.06

Allegro MicroSystems, LLC reserves the right to make, from time to time, such de p ar t ures from the detail spec i f i c a t ions as may be required to permit improvements in the per f or m ance, reliability, or manufacturability of its products. Before placing an order, the user is cautioned to verify that the information being relied upon is current.

Allegro’s products are not to be used in life support devices or systems, if a failure of an Allegro product can reasonably be expected to cause the failure of that life support device or system, or to affect the safety or effectiveness of that device or system.

The in f or m a t ion in c lud e d herein is believed to be ac c u r ate and reliable. How e v e r, Allegro MicroSystems, LLC assumes no re s pon s i b il i t y for its use; nor for any in f ringe m ent of patents or other rights of third parties which may result from its use.

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