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A High-Resolution Time-to-Digital Converter Implemented in Field-Programmable-Gate-Arrays

Jian Song,Qi An,and Shubin Liu

Abstract—A high-resolution time-to-digital converter(TDC) implemented in a general purpose?eld-programmable-gate-array (FPGA)is presented.Dedicated carry lines of an FPGA are used as delay cells to perform time interpolation within the system clock period and to realize the?ne time measurement.Two Gray-code counters,working on in-phase and out-of-phase system clocks respectively,are designed to get the stable value of the coarse time measurement.The?ne time code and the coarse time counter value,along with the channel identi?er,are then written into a ?rst-in?rst-out(FIFO)buffer.Tests have been done to verify the performance of the TDC.The resolution after calibration can reach50ps.

Index Terms—Field programmable gate arrays(FPGAs), time-to-digital converter(TDC),time measurement,code density test.

I.I NTRODUCTION

H IGH-resolution time measurement is essential in many

applications[1]–[3],and particularly in high-energy physics experiments[4]–[7].The ef?ciency of particle iden-ti?cation using the time-of-?ight(TOF)technique is directly related to the precision of time measurement.For example,in the BESIII project,the total time resolution of TOF counter should be better than85ps,and the total time resolution of the main drift chamber should not be more than500ps[8]. There are many approaches to improving the resolution of time measurements,such as time interpolation,time stretching, the vernier method,etc.[9]–[11].Among them,time interpola-tion is a straightforward way to get high resolution and a long dynamic range.Time interpolation requires delay elements, which may be delay cells of a delay locked loop(DLL),gate delay cells of an application-speci?c-integrated-circuit(ASIC), R-C delay lines of an ASIC,basic resources of a?eld-pro-grammable-gate-array(FPGA),dedicated resources of an FPGA,etc.All of these delay elements are either resources of an ASIC[1]–[7],[11]–[14]or resources of an FPGA[15]–[22]. Taking cost,development time,and?exibility into considera-tion,it is desirable to use an FPGA to implement a time-to-dig-ital converter(TDC).Much work has been done in this?eld [15]–[22].In1995,an FPGA-based approach was proposed by Kalisz,et al.[15].They made use of the difference between

Manuscript received September1,2005;revised November4,2005.This work was supported in part by the National Natural Science Foundation of China(NSFC)under Grant10405023and the Graduate Innovation Foundation of USTC under Grant KD2004011.

Jian Song,Qi An,and Shubin Liu are with the Fast Electronics Laboratory, Department of Modern Physics,University of Science and Technology of China (USTC),Hefei230026,China(e-mail:jeansong@https://www.wendangku.net/doc/f014930502.html,).

Digital Object Identi?er10.1109/TNS.2006.869820a latch delay and a buffer delay of QuickLogic’s FPGA and achieved a time resolution of100ps[16].In2002,Andaloussi, et al.reported a novel TDC architecture based on a two-di-mensional time delay matrix[17].The architecture was imple-mented in a XCV3000Virtex FPGA from Xilinx.The resulting TDC allowed for time measurements over a21ms range with a150ps resolution.In the same year,Fries,et al.realized a TDC in an FPGA using a192MHz quadrature clock[18].This implementation achieved a resolution of better than1.4ns.In 2003,a TDC was implemented in an ACEX1K FPGA from Altera by Wu,et al.[19].This TDC used cascade chains of the FPGA and offered a time resolution of about400ps.In the same year,Zielinski,et al.implemented a high-resolution time in-terval measuring system in a single FPGA device[20].The bin size of the system was500ps.In2004,a TDC with75ps single shot resolution was implemented in an FPGA from Xilinx by Xie,et al.[21].The TDC was based on a counter and a two step cascading delay line.In the same year,Szymanowski,et al.im-plemented a high-resolution TDC with two stage interpolators in a QL12X16B from QuickLogic[22].The TDC had200ps resolution and standard measurement uncertainty below140ps. Some previous work on time measurement has been done in our laboratory[23]–[28].In2002,a TDC was implemented in a Virtex-II FPGA from Xilinx by using twelve digital clock managers(DCM)for phase shifting.In2003,a prototype board for the TOF system of the BESIII project,with a resolution reaching17ps,was designed using a high-performance time-to-digital converter designed by CERN/EP-MIC[13].Now we are designing the?nal boards for the TOF system of the BESIII project.In2004,a TDC was implemented for these in a gen-eral purpose FPGA device by using dedicated carry lines in the FPGA to perform time interpolation.

II.A RCHITECTURE

In the general purpose FPGAs from Altera and Xilinx,there are many dedicated carry lines,which connect adjacent basic logic elements.These dedicated carry lines are normally used to form dedicated carry chains to implement arithmetic func-tions such as fast adders,counters,and comparators.The delay of each carry line is short and can be considered?xed for a par-ticular physical technology,rail voltage,and temperature range. Using these carry lines as delay cells,a high-resolution TDC can be implemented in an FPGA.

To verify our idea of time interpolation within one clock pe-riod using dedicated carry lines,a simpli?ed TDC based on counter and time interpolation methods was implemented in an FPGA.The block diagram of the simpli?ed TDC is shown in Fig.1.

0018-9499/$20.00?2006IEEE

Fig.1.Block diagram of the time-to-digital converter implemented in a single FPGA

device.

Fig.2.Diagram of the carry chain of a multibit adder.

A.Fine Time Measurement

One of the simplest forms used to combine the dedicated carry lines into a carry chain is a multibit adder.The Boolean equations of each adder cell

are:

(1)

where A and B are inputs for the adder,Ci is a carry-in bit,Co is a carry-out bit,and Sum is a sum bit.

The diagram of the carry chain using a multibit adder is shown in Fig.2.The delay time of the whole chain must be longer than one period of the system clock.We set all A to logic one and all B except the least signi ?cant bit (LSB)to logic zero.The LSB of B is the hit signal.If there is no hit signal,all Sum would be logic one.When there is a hit signal,each bit of the sum,from the LSB to the most signi ?cant bit (MSB),will change to logic zero step by step.The changed bits indicate the elapsed time of the hit signal passing along the carry chain.At the next rising edge of the system clock the sum bits will be latched.This is the ?ne time measurement in a thermometer code.

While trying to latch the adder ’s output bits at the rising edge of the system clock,we use dual synchronizers to reduce the probability of metastability [29]–[31].There are many kinds of conversion schemes to convert a thermometer code to a natural binary code for the ?ne time measurement.The binary-search encoder is chosen for its simplicity and easy implementation [32].

In the ?ne time measurement,it is very important to keep a uniform delay between the bits of the sum to the input of their corresponding register.A basic logic element that contains a look-up table (LUT)and a programmable register is used to form the 1-bit adder which generates the sum bit and the reg-ister for latching the sum bit.In addition,constraints must be set in the design tool and sometimes logic cells must be placed manually.

B.Coarse Time Counter

A synchronous counter is designed to realize the coarse time measurement.The counter may change its state while the hit

ar-

Fig.3.Coarse time counter.(a)Architecture of the coarse time counter.(b)Timing of the coarse time counter.

rives.To avoid ambiguous states,two Gray-code counters run-ning at the system clock rate (one in phase and another out of phase)are used as shown in Fig.3,[11],[13],[33].Depending on the phase of the system clock at the arrival moment of the hit signal,one of the two counter ’s outputs is selected and en-coded with a binary code as the coarse time measurement code.

If the hit arrives in the ?rst

half

of the system clock pe-riod,the output of the “in phase ”counter is selected.Otherwise the output of the “out of phase ”counter is selected.The result of the ?ne time measurement re ?ects the phase of the system https://www.wendangku.net/doc/f014930502.html,ing the result of the ?ne time measurement,a stable coarse time count value is always obtained.C.Read-Out Buffer

The result of the complete time measurement (the ?ne time and the coarse time measurement)is written into a ?rst-in ?rst-out (FIFO)buffer along with a channel identi ?er.The total time measurement can be expressed as

follows:

(2)

where

is the result of the complete time

measurement,is the result of the coarse time

measurement,is

the result of the ?ne time

measurement,

is the period of the system

clock,

is the coarse time measurement

code,is the bin size (the LSB value)of the ?ne time measurement,

and is the ?ne time measurement code.

III.T EST R ESULTS

The delay time of a dedicated carry line is different in FPGA ’s from different companies,series,capacity,and speed-grade.An EP1K50TC144-1ACEX 1K FPGA device from Altera [34]and a XC2V4000-6BF957Virtex-II FPGA device from Xilinx [35]were selected to implement TDC design.

A test board based on a Versa Module Eurocard (VME)plat-form was designed to test the performance of the TDCs.The test was made at an ambient temperature of around 20C and with nominal supply voltages.We used the typical statistical test method based on a large number of measurements [11],[36].Characterization of the differential and integral nonlinearities

was performed using the statistical code density test [11]–[13],[36].The measurement of cable delay was used to evaluate the overall resolution [3],[13],[16].The maximum standard devi-ation value of different cable delay measurements is the min-imum measurable time interval resolution of the TDC.Active carry lines are lines for which the total delay time until that line is less than or equal to one clock period.The numbers of ac-tive carry lines at different clock rates were used to estimate the propagation delay time per delay cell,i.e.,the bin size of the ?ne time measurement.For instance,the number of active

delay cells

is

when the clock period

is ,and the number of active delay cells

is

when the clock period

is .Then,the bin size would

be

.The coarse time counters run circularly at the system clock and without external synchronization the coarse time counter value is a relative value,not an absolute value.Furthermore,the differential linearity of the coarse counter can reach 0.05%in the dynamic range according to the test.So tests are focused on the ?ne time measurements.

A.Performance of TDC Implemented in FPGA of Altera A 6-channel TDC was designed in an Altera ACEX 1K FPGA.The number of active carry lines is 69at 128MHz clock frequency,and the number of active carry lines is 44at 200MHz clock frequency.So the bin size is 112.5ps.The clock frequency in the performance tests is 136MHz.The linearity of one of the channels is shown in Figs.4(a)and (b)from a data set of more than 500000random hits.Other channels ’performances are similar.The time interval resolution from a data set of more than 50000measurement times is shown in Fig.4(c).The obtained differential nonlinearity (DNL)is

between

and bins,and the obtained integral nonlinearity (INL)is in the range

of

bins.The time interval resolution is 129.4ps.So the resolution of the TDC

is ps.

From Fig.4(a)and (b),a periodical phenomenon of INL and DNL can be noticed.It can be explained by some features in the architecture of this FPGA [34].In Altera ACEX 1K FPGAs,a single logic array block (LAB)is automatically used to imple-ment a carry chain of up to eight logic elements (LE).For longer chains,several LABs are automatically linked.Also,linking every other LAB in a row to form a long carry chain as the default setting of the compiler can enhance ?tting.That is to say,a carry chain longer than one LAB skips either from even-numbered LAB to even-numbered LAB,or from odd-numbered LAB to odd-numbered LAB.The delay time of the carry line between LABs is longer than the one between logic elements,which leads to the nonuniformity of the delay cells.This fea-ture is inherent to the architecture,and a calibration scheme to compensate for this systematic nonuniform delay could be en-visaged.

B.Performance of TDC Implemented in FPGA of Xilinx A 32-channel TDC was designed in a Xilinx Virtex-II FPGA.Here,two carry lines are regarded as one delay cell due to the characteristics of the FPGA structure.The number of active delay cells is 144at 96MHz clock frequency,and the number

of

Fig.4.Performance of the ?ne time measurement of the TDC implemented in the FPGA of Altera.(a)Differential nonlinearity.(b)Integral nonlinearity.(c)Time interval resolution.

active delay cells is 138at 100MHz clock frequency.So the bin size is 69.5ps.The clock frequency in the performance tests

is96MHz.The linearity of one of the channels is shown in Fig.5(a)and(b)from a data set of more than2000000random hits.Other channels’performances are similar.The time in-terval resolution from a data set of more than50000measure-

ment times is shown in Fig.5(c).The obtained DNL is

between

and bins,and the obtained INL is in the range

of

bins.The time interval resolution is93.1ps.

So the resolution of the TDC

is ps.

The nonlinearity is mainly caused by the architecture of the

Xilinx FPGA,more exactly,the different distribution delays

of the clock[35].The clock distribution of a XC2V4000-6is

shown in Fig.6.The clock signal is?rst transferred from a clock

pin to a buffer in the center of the FPGA,and then fanned out

by the buffer to local nodes which provide the clock to nearby

slices.The delay from the buffer to each node is not uniform,

and the load on each local clock tree net is different.So there

may be a signi?cant difference of the distribution delay time be-

tween neighboring slices whose clocks are from different nodes.

For example,there is39ps distribution delay time difference be-

tween the47th slice(1.474ns)and the48th slice(1.435ns).This

is inevitable when using a high-density FPGA,yet the error of

linearity by the distribution delay is systematic and can be partly

compensated for in calibration.A low-density FPGA could also

implement a TDC if we only consider the implementation.But

the length of the carry chain,which is restricted by the low den-

sity,will demand an increase of the system clock frequency and

therefore cause other dif?culties in system design.

IV.D ISCUSSIONS

A.Temperature and Voltage

The devices are commercial and operate in a temperature

range between0C and85 C.The performance of the TDCs

was examined over the temperature range from10C to30 C.

The performance almost doesn’t vary with temperature.Also,

the performance doesn’t vary

within%range of the normal

supply voltage.It is expected that the performance of the TDCs

will change little with temperatures and supply voltages inside

the operating ranges[5],[15],[16],[19],[21].Further tests will

be carried out later.

B.Calibration and Resolution

Many effects could in?uence the performance of the TDCs.

Some of them are systematic and inherent to the architecture

of the device being used.As pointed out before,we can partly

compensate for them and perform calibration to obtain higher

time resolutions by using the results of the statistical code den-

sity test[9],[11]–[13],[37].The time interval resolution after

calibration of the Altera ACEX1K device is91.9ps.So the res-

olution of the TDC

is ps.The time interval res-

olution after calibration of the Xilinx Virtex-II device is65.3ps.

So the resolution of the TDC

is ps.The cali-

bration constants can be considered stable at temperatures from

10C to30C

and%supply voltage variations.Better reso-

lutions would be obtained if comparator devices or other means

had been used to get a higher slew rate and lower jitter of the

input signals[29],[37],

[38].

Fig.5.Performance of the?ne time measurement of the TDC implemented

in the FPGA of Xilinx.(a)Differential nonlinearity.(b)Integral nonlinearity.

(c)Time interval resolution.

C.Dead Time

The architecture of a TDC implemented in an FPGA can

be adapted to meet various dead time goals under multihit sit-

uations.The dead time can be reduced to one period of the

游标卡尺读数方法

游标卡尺和螺旋测微器 1、游标卡尺的组成及分类 尺寸常用游标卡尺或千分尺测量,卡尺的组成,游标卡尺的式样很多,常用的有两用游标卡尺和双面游标卡尺。 2、游标卡尺的分类 以测量精度上分又有0.1㎜(游标尺10格)精度游标卡尺,0.05(游标尺20格)精度游标卡尺和0.02(游标尺50格)精度游标卡尺。 3、游标卡尺的刻线原理 (1)0.1㎜(1/10)精度游标卡尺刻线原理 尺身每小格为1㎜,游标刻线总长为9㎜,并等分为10格,因此每格为9/10=0.9㎜,则尺身和游标相对一格之差为1-0.9=0.1㎜,所以它的测量精度为0.1㎜。 (2)0.05㎜(1/20)精度游标卡尺刻线原理 尺身每小格为1㎜,游标刻线总长为39㎜,并等分为20格,因此每格为39/20=1.95㎜,则尺身和游标相对一格之差为2-1.95=0.05㎜,所以它的测量精度为0.05㎜。 (3)0.02㎜(1/50)精度游标卡尺刻线原理 尺身每小格为1㎜,游标刻线总长为49㎜,并等分为50格,因此每格为49/50=0.98㎜,则尺身和游标相对之差为1-0.98=0.02㎜,所以它的测量精度为0.02㎜。 4、游标卡尺读数方法: 读数时首先以游标零刻度线为准在尺身上读取毫米整数,即以毫米为单位的整数部分。然后看游标上第几条刻度线与尺身的刻度线对齐,如第6条刻度线与尺身刻度线对齐,则小数部分即为0.6毫米(若没有正好对齐的线,则取最接近对齐的线进行读数)。 判断游标上哪条刻度线与尺身刻度线对准,可用下述方法:选定相邻的三条线,如左侧的线在尺身对应线左右,右侧的线在尺身对应线之左,中间那条线便可以认为是对准了。 5、游标卡尺的使用游标卡尺可用来测量工件的宽度、外径、内径和深度。 6、螺旋测微器

游标卡尺原理与使用.

游标卡尺使用说明书 游标卡尺的结构 游标卡尺是工业上常用的测量长度的仪器,它由尺身及能在尺身上滑动的游标组成,如图2.3-1所示。若从背面看,游标是一个整体。游标与尺身之间有一弹簧片(图中未能画出,利用弹簧片的弹力使游标与尺身靠紧。游标上部有一紧固螺钉,可将游标固定在尺身上的任意位置。尺身和游标都有量爪,利用内测量爪可以测量槽的宽度和管的内径,利用外测量爪可以测量零件的厚度和管的外径。深度尺与游标尺连在一起,可以测槽和筒的深度。 尺身和游标尺上面都有刻度。以准确到0.1毫米的游标卡尺为例,尺身上的最小分度是1毫米,游标尺上有10个小的等分刻度,总长9毫米,每一分度为0.9毫米,比主尺上的最小分度相差0.1毫米。量爪并拢时尺身和游标的零刻度线对齐,它们的第一条刻度线相差0.1毫米,第二条刻度线相差0.2毫米,……,第10条刻度线相差1毫米,即游标的第10条刻度线恰好与主尺的9毫米刻度线对齐,如图2.3-2。

当量爪间所量物体的线度为0.1毫米时,游标尺向右应移动0.1毫米。这时它的第一条刻度线恰好与尺身的1毫米刻度线对齐。同样当游标的第五条刻度线跟尺身的5毫米刻度线对齐时,说明两量爪之间有0.5毫米的宽度,……,依此类推。 在测量大于1毫米的长度时,整的毫米数要从游标“0”线与尺身相对的刻度线读出。 游标卡尺的使用 用软布将量爪擦干净,使其并拢,查看游标和主尺身的零刻度线是否对齐。如果对齐就可以进行测量:如没有对齐则要记取零误差:游标的零刻度线在尺身零刻度线右侧的叫正零误差,在尺身零刻度线左侧的叫负零误差(这件规定方法与数轴的规定一致,原点以右为正,原点以左为负。 测量时,右手拿住尺身,大拇指移动游标,左手拿待测外径(或内径的物体,使待测物位于外测量爪之间,当与量爪紧紧相贴时,即可读数,如图2.3-3所示。 游标卡尺的读数 读数时首先以游标零刻度线为准在尺身上读取毫米整数,即以毫米为单位的整数部分。然后看游标上第几条刻度线与尺身的刻度线对齐,如第6条刻度线与尺身刻度线对齐,则小数部分即为0.6毫米(若没有正好对齐的线,则取最接近对齐的线进行读数。如有零误差,则一律用上述结果减去零误差(零误差为负,相当于加上相同大小的零误差,读数结果为:

游标卡尺及万能角度尺的使用说明(有图示)

游标卡尺及万能角度尺的使用说明(有图示)

一、游标卡尺的使用说明 利用游标原理对两测量面相对移动分隔的距离进行读数的测量器具。游标卡尺(简称卡尺)。 游标卡尺可以测量产品的内、外尺寸(长度、宽度、厚度、内径和外径),孔距,高度和深度等。 游标卡尺根据其结构可分单面卡尺、双面卡尺、三用卡尺等。 (1)单面卡尺带有内外量爪,可以测量内侧尺寸和外侧尺 寸(图1-1)。 (2)双面卡尺的上量爪为刀口形外量爪,下量爪为内外量爪,可测 内外尺寸(图1-2)。 (3)三用卡尺的内量爪带刀口形 ,用于测量内尺寸;外量爪带平面 和刀口形的测量面,用于测量外尺寸;尺身背面带有深度尺,用于测量深度和高度(图1-3)。 (4)标卡尺读数原理与读数方法 为了掌握游标卡尺的正确使用方法,必须学会准确读数和正确操作。 游标卡尺的读数装置,是由尺身和游标两部分组成,当尺框上的活动测量爪与尺身上的固定测量爪贴合时,尺框上游标的“0”刻线(简称游标零线)与尺身的“0”刻线对齐,此时测量爪之间的距离为零。测量时,需要尺框向右移动到某一位置,这时活动测量爪与固定测量爪之间的距离,就是被测尺寸,见图1-4。假如游标零线与尺身上表示30mm 的刻线正好对齐,则说明被测尺寸是30mm ;如果游标零线在尺身上指示的尺数值比30mm 大一点,应该怎样读数呢?这时,被 刀口内测量爪 尺身尺框紧固螺钉 游标深度尺外测量爪图1-3

测尺寸的整数部分(为30mm),如上所述可从游标零线左边的尺身刻线上读出来 (图中箭头所指刻线),而比1mm小的小数部分则是借助游标读出来的(图中● 图1-4:游标卡尺测量尺寸 游标的小数部分读数方法是首先看游标的哪一条线与尺身刻线对 齐;然后把游标这条线的顺序数乘以游标读数值,就得出游标的读数,即 游标的读数=游标读数值X游标对齐刻线的顺序数 游标卡尺读数时可分三步: A、先读整数——看游标零线的左边,尺身上最靠近的一条刻线的数值,读出被测尺寸的整数部分; B、再读小数——看游标零线的右边,数出游标第几条刻线与尺身的数值刻线对齐,读出被测尺寸的小数部分(即游标读数值乘其对齐刻线的顺序数); C、得出被测尺寸——把上面两次读数的整数部分和小数 部分相加,就是卡尺的所测尺寸。 (1)注意事项 A、清洁量爪测量面。 B、检查各部件的相互作用;如尺框和微动装置移动灵活,紧固螺钉能否起作用。 C、校对零位。使卡尺两量爪紧密贴合,应无明显的光隙,主尺零线与游标尺零线应对齐。 D、测量结束要把卡尺平放,尤其是大尺寸的卡尺更应该注意,否则尺身会弯曲变形。 E、带深度尺的游标卡尺,用完后,要把测量爪合拢,否侧较细的深度尺露在外边,容易变形甚至折断。 F、卡尺使用完毕,要擦净上油,放到卡尺盒内,注意不要锈 蚀或弄脏。

游标角度尺使用说明

游标角度尺(0-320°2′) 在机械制造过程中及计量仪器校准中,有许多带角度的工件需要测量,而测量角度的方法与量具有多种多样的选择,使用游标万能角度尺来测量工件角度是比较方便的,如(图A)所示。 一.读数方法 ①先读度数:被游标尺零刻线所指的主尺上刻线是表示被测工件测量角的度数。 ②再读分数:与主尺上刻线重合的游标尺上刻线是被测工件测量角的分数。 ③相加求得测量值:将被测工件测量角的度数与分数相加起来,即为被测角度值。 二.结构与用途 游标万能角度尺的结构如(图A)所示。角尺和直尺在卡块的作用下分别固定于扇形板部件和角尺上,当转动卡块上的螺帽时,即可紧固或放松角尺或直尺,在扇形板部件的后面有一与齿轮杆相连接的手把,而该齿轮杆又与固定在主尺上的弧形齿板相啮合这个就是微动装置。当转动微动装置就能使主尺和游

标尺作细微的相对移动,以精确地调整测量值,但当把制动头上的螺帽拧紧后,则扇形板部件与主尺被紧固在一起,而不能有任何相对移动。 游标万能角度尺主要用于测量各种形状工件与样板的内、外角度以及角度划线。 三.使用和注意事项 1.零值检查:使用前将游标万能角度尺擦拭干净,检查各部分相互作用是否灵活可靠,然后移动直尺使其与基尺的测量面相互接触,直到无光隙可见为止。同时观察主尺零刻线与游标零刻线是否对准;游标尺的尾刻线与主尺相应刻线是否对准,如对准便可使用,不对准则需要调整。 2.测量0°~50°之间的角度时,被测工件放在基尺和直尺的测量面之间,如图(B-4)所示。 3.测量50°~140°之间的角度时,把角尺取下,将直尺换在角尺位置上,把被测工件放在基尺和直尺的测量面之间,如图(B-1),(B-2)所示。

游标卡尺读法大全

游标卡尺的快速正确的读数方法 游标卡尺是科研和工程技术上常用的的比较精确的长度测量工具。它的正确使用和准确读数是历届高考的热点。下面介绍游标卡尺的一种快速正确的读数方法。 游标卡尺的读数公式推导: 设某次测量物体的长度的情况如图1所示,其中 L 1为主尺的零刻度线到游标尺的零刻度线之间的整毫 米数,设有a 小格,则为a 毫米;L 2是主尺上紧靠游 标尺前的整毫米刻度线到与游标尺对齐的刻度线之间 的长度,设有b 小格,则为b 毫米;L 3是游标尺上的 零刻度线到游标尺上与主尺对齐的刻度线之间的长 度,设有c 小格;主尺零刻度线到游标尺零刻度线之 间的长度等于待测物体的长度为L 。则有: x a L L L L 321+=-+= 其中a 是以毫米为单位读数的整数部分;x 是以毫米为单位读数的小数部分,显然有:32L L x -=。 设游标尺总的长度为m 毫米,有n 个等分小格,每1小格的长度等于n m 毫米。50等分的游标尺长度为49毫米,20等分的游标尺长度为19毫米,10等分的游标尺长度为9毫米,这类游标卡尺,有1n m -=。另外有一种10等分的游标尺长度为19mm ,则1n 2m -=。 则n m c b L L x 32? -=-=, 当1n m -=时, )n 11(c b n m c b x --=?-=, 这类游标卡尺,实践中发现c b =,即主尺上紧靠游标尺的零刻度线前毫米刻度线到与游标尺对齐的刻度线的毫米数b ,等于游标尺上的零刻度线到游标尺与主尺对齐的刻度线之间的小格数c 是相等的。则有: n 1c x ?=。 当1n 2m -=时, )n 12(c b n m c b x --=?-=, 对这种游标卡尺,实验中发现,c 2b =。则同样有: n 1c x ?=。

游标卡尺读法大全

游标卡尺是利用主尺刻度间距与副尺刻度间距读数的。 游标卡尺读数分为三个步骤,下面以所插入的下图所示0.02游标卡尺的某一状态为例进行说明: 1.在主尺上读出副尺零线以左的刻度,该值就是最后读数的整数部分。图示33mm。 2.副尺上一定有一条与主尺的刻线对齐,在刻尺上读出该刻线距副尺的格数,将其与刻度间距0.02mm相乘,就得到最后读数的小数部分。图示为0.24mm。 3.将所得到的整数和小数部分相加,就得到总尺寸为33.24mm。 使用游标卡尺测量零件尺寸时,必须注意下列几点: 1.测量前应把卡尺揩干净,检查卡尺的两个测量面和测量刃口是否平直无损,把两个量爪紧密贴合时,应无明显的间隙,同时游标和主尺的零位刻线要相互对准。这个过程称为校对游标卡尺的零位。 2.移动尺框时,活动要自如,不应有过松或过紧,更不能有晃动现象。用固定螺钉固定尺框时,卡尺的读数不应有所改变。在移动尺框时,不要忘记松开固定螺钉,亦不宜过松以免掉了。 3.当测量零件的外尺寸时:卡尺两测量面的联线应垂直于被测量表面,不能歪斜。测量时,可以轻轻摇动卡尺,放正垂直位置。先把卡尺的活动量爪张开,使量爪能自由地卡进工件,把零件贴靠在固定量爪上,然后移动尺框,用轻微的压力使活动量爪接触零件。如卡尺带有微动装置,此时可拧紧微动装置上的固定螺钉,再转动调节螺母,使量爪接触零件并读取尺寸。决不可把卡尺的两个量爪调节到接近甚至小于所测尺寸,把卡尺强制的卡到零件上去。这样做会使量爪变形,或使测量面过早磨损,使卡尺失去应有的精度。 4.用游标卡尺测量零件时,不允许过分地施加压力,所用压力应使两个量爪刚好接触零件表面。如果测量压力过大,不但会使量爪弯曲或磨损,且量爪在压力作用下产生弹性变形,使测量得的尺寸不准确(外尺寸小于实际尺寸,内尺寸大于实际尺寸)。 在游标卡尺上读数时,应把卡尺水平的拿着,朝着亮光的方向,使人的视线尽可能和卡尺的刻线表面垂直,以免由于视线的歪斜造成读数误差。 5.为了获得正确的测量结果,可以多测量几次。即在零件的同一截面上的不同方向进行测量。对于较长零件,则应当在全长的各个部位进行测量,务使获得一个比较正确的测量结果。

游标卡尺的正确使用方法介绍

游标卡尺的正确使用方法介绍

游标卡尺 游标卡尺是工业上常用的测量长度的仪器,它由尺身及能在尺身上滑动的游标组成,若从背面看,游标是一个整体。游标与尺身之间有一弹簧片(图中未能画出),利用弹簧片的弹力使游标与尺身靠紧。游标上部有一紧固螺钉,可将游标固定在尺身上的任意位置。尺身和游标都有量爪,利用内测量爪可以测量槽的宽度和管的内径,利用外测量爪可以测量零件的厚度和管的外径。深度尺与游标尺连在一起,可以测槽和筒的深度。 机械游标卡尺的简介: 游标卡尺是精密的长度测量仪器,常见的机械游标卡尺如下图所示。它的量程为0~110mm,分度值为0.1mm,由内测量爪、外测量爪、紧固螺钉、微调装置、主尺、游标尺、深度尺组成。

0~200mm以下规格的卡尺具有测量外径、内径、深度三种功能: 游标卡尺的零位校准: 步骤1:使用前,松开尺框上坚固螺钉,将尺框平稳拉开,用布将测量面、导向面擦干净; 步骤2:检查“零”位:轻推尺框,使卡尺两个量爪测量面合并,观察游标“零”刻线与尺身“零”刻线应对齐,游标尾刻线与尺身相应刻线应对齐。否则,应送计量室或有关部门调整。

游标卡尺的测量方法:(外径) 1、传统人工读数方法 步骤1:将被测物擦干净,使用时轻拿轻放; 步骤2:松开千分尺的固紧镙钉,校准零位,向后移动外测量爪,使两个外测量爪之间距离略大于被测物体; 步骤3:一只手拿住游标卡尺的尺架,将待测物置于两个外测量爪之间,另一手向前推动活动外测量尺,至活动外测量尺与被测物接触为止。 步骤4:读数。 注意:1)测量内孔尺寸时,量爪应在孔的直径方向上测量。 2)测量深度尺寸时,应使深度尺杆与被测工件底面相垂直。 2、利用数据采集仪连接游标卡尺实现高效测量法 当前工厂内部品质检查的方法为测量一个数据后,由测量人员人工记录在纸张中,或者由一个人测量,另一个人进行记录的操作方式,当需要进行分析时,由操作人员录入到电脑的EXCEL表格中;目前方式导致的问题是效率低,数据容易记错,同时有些操作人员由于不清楚产品的测量规格,对于产品超过规格的情况,操作人员不能及时采取措施,而且对于需要进行数据分析时,还需要重复录入电脑中。 利用数据采集仪连接游标卡尺来进行测量,数据采集仪会自动采集测量数据并计算分析、自动判断结果,这种测量方法可以提高测量效率,减少由于人工测量所造成的误差,效果如下图所示:

游标卡尺的原理及使用方法

一、游标卡尺的原理及使用方法 游标卡尺是工业上常用的测量长度的仪器,它由尺身及能在尺身上滑动的游标组成。若从背面看,游标是一个整体。游标与尺身之间有一弹簧片,利用弹簧片的弹力使游标与尺身靠紧。游标上部有一紧固螺钉,可将游标固定在尺身上的任意位置。尺身和游标都有量爪,利用内测量爪可以测量槽的宽度和管的内径,利用外测量爪可以测量零件的厚度和管的外径。深度尺与游标尺连在一起,可以测槽和筒的深度。 1.游标卡尺的使用 论①用软布将量爪擦干净,使其并拢,查看游标和主尺身的零刻度线是否对齐。如果对齐就可以进行测量:如没有对齐则要记取零误差:游标的零刻度线在尺身零刻度线右侧的叫正零误差,在尺身零刻度线左侧的叫负零误差(这件规定方法与数轴的规定一致,原点以右为正,原点以左为负)。 ②测量时,右手拿住尺身,大拇指移动游标,左手拿待测外径(或内径)的物体,使待测物位于外测量爪之间,当与量爪紧紧相贴时,即可读数。 2.游标卡尺的读数 读数时首先以游标零刻度线为准在尺身上读取毫米整数,即以毫米为单位的整数部分。然后看游标上第几条刻度线与尺身的刻度线对齐,如第6条刻度线与尺身刻度线对齐,则小数部分即为0.6毫米(若没有正好对齐的线,则取最接近对齐的线进行读数)。如有零误

差,则一律用上述结果减去零误差(零误差为负,相当于加上相同大小的零误差),读数结果为: L=整数部分+小数部分-零误差 二、数显游标卡尺的原理及使用方法 该卡尺是采用容栅传感器,并配以大规模集成电路和液晶显示的一种测量工具,它由一节3V扣式电池供电,可直接从卡尺零位或某一给定零测量尺寸(即绝对测量或相对测量)。该卡尺应用范围广,使用方便,无视觉误差。可用于外尺寸和内尺寸的测量,也可进行台阶及深度尺寸的测量。 具有任意位置测量单位转换、任意位置置零、带电源开关及数据输出等功能。 1.分辨率:0.01mm/0.0005in 2.注意事项:①开始使用前,用干燥清洁的布(可沾少许清洁油)反 复轻擦保护膜表面。 ②在卡尺的任何部位不能施加电压,也不要用电笔刻字, 以免损坏电子元件。 ③不使用时断开电源或取出电池。 3.测量方法:①按电源开关键(OFF/ON),打开电源; ②按测量单位键(mm/inch),选择所需单位制。 ③移动尺框,使两外测量面手感接触后按置零键 (ZERO)置零,即可进行正常测量。 ④测量完毕后,按电源开关键(OFF/ON),关闭电源。

游标卡尺的认识及使用

图2 游标卡尺是一种比较精密的量具,在测量中用得最多。通常用来测量精度较高的工件,它可测量工件的外直线尺寸、宽度和高度,有的还可用来测量槽的深度。如果按游标的刻度值来分,游标卡尺又分0.1、0.05、0.02mm三种。 2卡尺的认识 对于游标尺上有10个等分小格的,是精确度0.1毫米的游标卡尺,游标尺的刻度如图3所示。这种游标尺的第几条刻度线与主尺的某条刻度线对齐就读零点几毫米,第0条、第1条、第2、第3条、第4条、第5条、第6条、第7条、第8条、第9条,它们对应的读数分别就是:0.0、0.1、0.2、0.3、0.4、0.5、0.6、 0.7、0.8、0.9、0.0mm 。

对于游标尺上有20个等分小格的,是精确到0.05毫米的游标卡尺,游标尺的刻度如图4所示。 对于游标尺上有50个等分小格的,是精确到0.02毫米的游标卡尺,游标尺的刻度如图5所示。 游标尺上从零刻度线开始,每隔5小格的刻度线分别标上数字1、2、3、4、5、6、7、8、9、0。从游标尺的零刻度线开始,各条刻度线与主尺某条刻度线对齐时,所对应的读数分别是:0.00、0.02、0.04、0.06、0.08、0.10、0.12mm,如此等等,直到0.90、0.92、0.94、0.96、0.98、0.00 mm。例如,当游标尺的第20条刻度线与主尺上的某条刻度线正对时,游标尺上的读数就是0.40mm,游标尺上的哪条刻度线刚好就是标有数字4的刻度线,当游标上尺上标有数字4的刻度线右边的第1条刻度线与主尺。 3游标卡尺的读数原理: 读数时首先以游标零刻度线为准在尺身上读取毫米整数,即以毫米为单位的整数部分。然后看游标上第几条刻度线与尺身的刻度线对齐,如第6条刻度线与尺身刻度线对齐,则小数部分即为0.6毫米(若没有正好对齐的线,则取最接近对齐的线进行读数)。如有零误差,则一律用上述结果减去零误差(零误差为负,相当于加上相同大小的零误差),读数结果为: L=整数部分+小数部分-零误差 游标卡尺是利用主尺刻度间距与副尺刻度间距读数的。以图6 0.02mm游标卡尺为例,主尺的刻度间距为1mm,当两卡脚合并时,主尺上49mm刚好等于副尺上50格,副尺每格长为= 0.98mm。主尺与副尺的刻度间相关为1-0398=0.02mm,因此它的测量精度为0.02mm(副尺上直接用数字刻出)游标卡尺读数分为三个步骤,下面以图13-3所示0.02游标卡尺的某一状态为例进行说明。1. 在主尺上读出副尺零线以左的刻度,该值就是最后读数的整数部分。 2. 副尺上一定有一条与主尺的刻线对

游标卡尺的结构及读数原理

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游标卡尺的结构和用法

游标卡尺的结构和用法 游标卡尺是工业上常用的测量长度的仪器,它由尺身及能在尺身上滑动的游标组成,如图2.3-1所示。若从背面看,游标是一个整体。游标与尺身之间有一弹簧片(图中未能画出),利用弹簧片的弹力使游标与尺身靠紧。游标上部有一紧固螺钉,可将游标固定在尺身上的任意位置。尺身和游标都有量爪,利用内测量爪可以测量槽的宽度和管的内径,利用外测量爪可以测量零件的厚度和管的外径。深度尺与游标尺连在一起,可以测槽和筒的深度。 尺身和游标尺上面都有刻度。以准确到0.1毫米的游标卡尺为例,尺身上的最小分度是1毫米,游标尺上有10个小的等分刻度,总长9毫米,每一分度为0.9毫米,比主尺上的最小分度相差0.1毫米。量爪并拢时尺身和游标的零刻度线对齐,它们的第一条刻度线相差0.1毫米,第二条刻度线相差0.2毫米,……,第10条刻度线相差1毫米,即游标的第10条刻度线恰好与主尺的9毫米刻度线对齐,如图2.3-2。

当量爪间所量物体的线度为0.1毫米时,游标尺向右应移动0.1毫米。这时它的第一条刻度线恰好与尺身的1毫米刻度线对齐。同样当游标的第五条刻度线跟尺身的5毫米刻度线对齐时,说明两量爪之间有0.5毫米的宽度,……,依此类推。 在测量大于1毫米的长度时,整的毫米数要从游标“0”线与尺身相对的刻度线读出。 游标卡尺的使用 用软布将量爪擦干净,使其并拢,查看游标和主尺身的零刻度线是否对齐。如果对齐就可以进行测量:如没有对齐则要记取零误差:游标的零刻度线在尺身零刻度线右侧的叫正零误差,在尺身零刻度线左侧的叫负零误差(这件规定方法与数轴的规定一致,原点以右为正,原点以左为负)。 测量时,右手拿住尺身,大拇指移动游标,左手拿待测外径(或内径)的物体,使待测物位于外测量爪之间,当与量爪紧紧相贴时,即可读数,如图2.3-3所示。 一、游标卡尺的读数 读数时首先以游标零刻度线为准在尺身上读取毫米整数,即以毫米为单位的整数部分。然后看游标上第几条刻度线与尺身的刻度线对齐,如第6条刻度

游标卡尺的读数原理和读数方法

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游标卡尺的正确使用(简洁版)

游标卡尺的使用 一、我们用什么仪器精确测量以下工件的内径外径和深度?

三、游标卡尺的用法: 1、握尺方法: 用手握住主尺,四个手指抓紧,大姆指按在 游标尺的右下侧半圆轮上,并用大姆指轻轻移动游 标使活动量爪能卡紧被测物体,略旋紧固定螺钉,再进行读数。 2、注意事项: 2.1 用量爪卡紧物体时,用力不能太大,否则会使测量不准确,并容易损坏卡尺。卡尺测量不宜在工件上随意滑动,防止量爪面磨损。 2.2 卡尺使用完毕,要擦干净后,将两尺零线对 齐,检查零点误差有否变化,再小心放入卡尺专用盒内,存放在干燥的地方。 四、读数原理: 二、游标卡尺的构造

1、游标读数值为0.1mm的游标卡尺 如图1(a)所示,主尺刻线间距(每格)为1mm,当游标零线与主尺零线对准(两爪合并)时,游标上的第10刻线正好指向等于主尺上的9mm,而游标上的其他刻线都不会与主尺上任何一条刻线对准。 游标每格间距=9mm÷10=0.9mm 主尺每格间距与游标每格间距相差=1mm-0.9mm=0.1mm 0.1mm即为此游标卡尺上游标所读出的最小数值,再也不能读出比0.1mm 小的数值。 当游标向右移动0.1mm时,则游标零线后的第1根刻线与主尺刻线对准。当游标向右移动0.2mm时,则游标零线后的第2根刻线与主尺刻线对准,依次类推。若游标向右移动0.5mm,如图1(b),则游标上的第5根刻线与主尺刻线对准。由此可知,游标向右移动不足1mm的距离,虽不能直接从主尺读出,但可以由游标的某一根刻线与主尺刻线对准时,该游标刻线的次序数乘其读数值而读出其小数值。例如,图1(b)的尺寸即为:5×0.1=0.5(mm)。 图1

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