dw8051
DesignWare Library
DW8051 MacroCell
Data Sheet
Overview
The DesignWare?DW8051?MacroCell is a high-performance, configurable, fully synthesizable 8051 core that is binary compatible with the industry standard 803x/805x microcontrollers. The DW8051 core is technology-independent and has been fabricated in both ASIC and FPGA technologies. Designed for ease of use, the DW8051 includes the coreConsultant?tool, a user-friendly wizard, which guides users through configuration, simulation and synthesis.
The DesignWare DW8051 MacroCell solution includes the DW8051 MacroCell, a reference design, and Synopsys’ extensive verification environment. The high-performance architecture of the DW8051 provides up to three times performance improvement over the standard 8051 when operating at the same clock rate.
Proven Quality, Complete Solution
To ensure quality, the DW8051 was developed according to Synopsys’ strict design-for-reuse methodology. It has undergone extensive testing during the design process and has been proven in many different technologies. It has also been tested with a variety of third-party 8051 development tools and 8051 evaluation boards.
The DW8051’s high-performance, config-urable, synthesizable architecture, combined with the development environment, provides a total solution for building low-cost, high-performance embedded control systems for a wide range of applications.Automated Design Flow with Synopsys coreConsultant
The DW8051 MacroCell solution includes the Synopsys coreConsultant tool, which provides the following services:
I Activity checklist that guides users
through DW8051 design activities in
the correct order
I Automatic, error-free DW8051
configuration,including parameter
cross-dependency checking
I Automatic configuration and operation
of the DW8051 verification environment I Automatic, high-quality synthesis with
users’ technology library and installed
version of Design Compiler?
I Automatic design checking and synthesis
results analysis
Users can operate coreConsultant in its GUI mode (Figure 1) or in batch mode through its command line interface.
Technical Advantages of the DW8051
I 4 clocks/instruction cycle versus 12 in
standard 8051
- Up to three times faster execution on
average versus standard 8051
I Stretch memory cycle
- Allows application software to adjust to
different external RAM speeds
- MOVX in as little as eight clock cycles I Dual data pointers
- Improves efficiency when moving large
blocks of data
I Internal/external peripheral interface
- Special function register (SFR) bus in
DW8051 supports both internal and
external peripherals vs. internal only in
standard 8051
I Two optional full-duplex serial ports
I Seven additional interrupts
I SFR bus for adding custom peripherals
803x/805x Compatibility
The DW8051 is compatible with the standard 8051 instruction set and can be configured to a wide range of industry standard 803x/805x architectures. Control signals for standard 803x/805x I/O ports are included. Optional full-duplex serial ports and third timer are selectable through parameters.High-Performance Architecture
The DW8051 is a fully static and synchronous
design. Eliminating wasted bus cycles and
providing dual data pointers for moving large
data blocks achieve greater efficiency and
performance. The DW8051 MacroCell
typically contains ~10k-13k gates, depending
on the configuration and technology in which
it is implemented. It runs at greater than 300
megahertz in 90-nm process technology.
Lower performance applications also benefit
by being able to run at lower clock rates to
get the same performance as a standard 12
clocks/instruction 8051. Lower clock rates
lead to lower power consumption and lower
electro-magnetic interference (EMI).
Adding Custom Designed Peripherals
A typical 8051 allows peripheral interface
only through port logic. In addition to the
ports, the DW8051 also provides direct
access to peripherals through the memory
and SFR buses (Figure 2).
I Users can interface additional peripherals
directly to the DW8051’s memory bus.
This method allows them to make use of
the “stretch” memory cycle feature to
interface slow peripherals.
I Users can also directly attach custom
designed peripherals to the efficient SFR
bus, the same bus used for interfacing the
standard DW8051 internal peripherals.
SFR addresses that are not used for the
DW8051 internal SFRs are available for
connecting external peripherals. Adding
peripherals to the SFR bus offers the
following advantages:
- Faster read, write accesses; 1 clock
vs. 2 clocks using mem_bus
- Direct addressing
- Takes advantage of bit
manipulation instructions
- Efficient, compact code
Third-Party Development Tools Support
Synopsys has an active program in place
to support third-party tools. Many industry
standard compilers, assemblers, ROM
monitors, and in-circuit emulators have been
tested for compatibility with the DW8051.
This allows integration of these tools into a
design environment and provides a complete
development solution for DW8051-based
embedded systems on a chip. Nohau
Corporation and Hitex Development Tools
provide in-circuit emulation support.
Figure 1. Example coreConsultant dialogs for DW8051
DW8051 Configurable Architecture Figure 3 illustrates the hardware architecture of the DW8051 core. The name of the
top-level module is DW8051_core. The internal RAM and ROM modules are located outside DW8051_core to facilitate simulation and insertion of technology-specific
RAM/ROM modules. The following
sub-modules and interfaces are selectable through parameter settings:
I DW8051_core can address either 128
or 256 bytes of internal RAM
I The internal ROM address range is deter-
mined by a parameter (rom_addr_size)
I Timer 2 (DW8051_timer2) is optional
I0,1, or 2 serial ports (DW8051_serial)
can be implemented
I The interrupt unit is either DW8051_intr_0
(6-source) or DW8051_intr_1 (13-source) The coreConsultant tool automatically generates the selected DW8051 configuration so that no HDL source code editing is needed.803X/805X Feature Comparison
Through parameter settings, user scan
configure the DW8051 hardware to be
functionally compatible with a variety of
803x/805x configurations. For example,
users can implement two 16-bit timers for
compatibility with the Intel 8051, or they
can implement three 16-bit timers for
compatibility with the Intel 80C32 (Table 1).
Performance Overview
The DW8051 processor core offers increased
performance by executing instructions in a
4-clock bus cycle, as opposed to the 12-clock
bus cycle in the standard 8051 (Figure 4).
The shortened bus timing improves the
instruction execution rate for most instructions
by a factor of three over the standard 8051
architectures.
Some instructions require a different number
of instruction cycles on the DW8051 than
the standard 8051. In the standard 8051,
all instructions except for MUL and DIV take
one or two instruction cycles to complete. In
the DW8051 architecture, instructions can
take between one and five instruction cycles
to complete. The average speed improvement
for the entire instruction set is approximately
two-and-a-half times (Table 2).
DW8051 Development Environment
The DW8051 MacroCell solution is devel-
oped and packaged for use with Synopsys’
coreConsultant tool. The complete DW8051
MacroCell solution coreKit includes:
I The DW8051 MacroCell
I Multiple-simulator support (e.g., VCS, MTI
ModelSim, Verilog-XL and NC-Verilog)
I An example 8032-compatible design
- This design uses the DW8051_core
and illustrates how to build and
connect 8051-compatible port modules
for designs where it is preferable to
use standard 8051 port modules
instead of the 16-bit address memory
interface
I Extensive verification environment
- HDL testbench that instantiates the
DW8051_core, models internal ROM
and RAM, and emulates 64-kilobytes
of external RAM and 64-kilobytes of
external ROM
- Processes that trace the program
counter and write accesses to
external RAM
(1) Internal ROM and RAM are located outside of DW8051_core.
Figure 3. DW8051_core Table 1. Feature summary of DW8051 and common
803x/805x configurations
- A collection of 8051 assembler
programs that test all of the instruction
set opcodes, plus miscellaneous tests
for internal hardware
- A set of expected results
(golden log files)
- Automatic testbench configuration,
simulation, and results checking
through coreConsultant
I Example scan insertion script for
Synopsys DFT Compiler?
I Example TSMC .18μm Library
I Complete documentation
- DW8051 data book in on-line format
(PDF), integrated into the
coreConsultant on-line help
I Support for third-party development tools
- Industry standard compilers,
assemblers, debuggers, ROM
monitors, in-circuit emulators from
Nohau and Hitex.
- Keil 8051 software development tools I Comprehensive worldwide technical
support About DesignWare IP
Synopsys’ DesignWare IP enables designers
to cost effectively create and verify complex
SoCs, ASICs and FPGAs. The broad IP
portfolio includes industry leading connec-
tivity IP Cores and Verification IP (e.g., USB
1.1,
2.0, OTG and PHYs, PCI, PCI-X?,PCI
Express?, PCI Express PHY, Ethernet,
1394, I2C), AMBA?on-chip bus (logic,
peripherals, verification IP) complete memo-
ry solution (e.g., memory controllers, BIST
and models), high-speed datapath compo-
nents, microcontrollers (8051, 6811)and
Star IP processors and DSP core (e.g.,
IBM PowerPC?440, Infineon C166?S and
TriCore?1, MIPS32?4KE?, NEC V850E?,
Philips CoolFlux?DSP). When combined
with our robust IP development methodology,
extensive investment in quality and comprehen-
sive worldwide technical support, DesignWare
IP gives designers a faster, more pre-
dictable and lower-risk path to chip success.
The DesignWare 8051 MacroCell is available
in encrypted form in the DesignWare Library.
The Source RTL of the DW8051 can also be
licensed individually, on a per-use basis
For a complete directory of Synopsys IP
visit: https://www.wendangku.net/doc/fb16578638.html,/ipdirectory
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Figure 4. Instruction cycle timing comparison
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Synopsys, the Synopsys logo, DesignWare and VCS are registered trademarks and coreConsultant, DW8051, Design Compiler and DFT Compiler, are
trademarks of Synopsys, Inc. PCI, PCI-X and PCI Express are trademarks of PCI-SIG. AMBA is a trademark of ARM Limited. All other products or service names
mentioned herein are trademarks of their respective holders and should be treated as such. Printed in the U.S.A.
?2004 Synopsys, Inc. 12/04.PS.WO.04-12879