I2C总线协议规范 v2.1
THE I2C-BUS SPECIFICATION
VERSION 2.1
JANUARY 2000
CONTENTS
1PREFACE. . . . . . . . . . . . . . . . . . . . . . . . . . .3 1.1Version 1.0 - 1992. . . . . . . . . . . . . . . . . . . . 3 1.2Version 2.0 - 198. . . . . . . . . . . . . . . . . . . . . 3 1.3Version 2.1 - 1999. . . . . . . . . . . . . . . . . . . . 3 1.4Purchase of Philips I2C-bus components . . 3 2THE I2C-BUS BENEFITS DESIGNERS
AND MANUFACTURERS. . . . . . . . . . . . . . .4 2.1Designer benefits . . . . . . . . . . . . . . . . . . . . 4 2.2Manufacturer benefits. . . . . . . . . . . . . . . . . 6 3INTRODUCTION TO THE I2C-BUS
SPECIFICATION . . . . . . . . . . . . . . . . . . . . .6 4THE I2C-BUS CONCEPT . . . . . . . . . . . . . . .6 5GENERAL CHARACTERISTICS . . . . . . . . .8 6BIT TRANSFER . . . . . . . . . . . . . . . . . . . . . .8 6.1Data validity . . . . . . . . . . . . . . . . . . . . . . . . 8 6.2START and STOP conditions. . . . . . . . . . . 9 7TRANSFERRING DATA. . . . . . . . . . . . . . .10 7.1Byte format . . . . . . . . . . . . . . . . . . . . . . . . 10 7.2Acknowledge. . . . . . . . . . . . . . . . . . . . . . . 10 8ARBITRATION AND CLOCK
GENERATION . . . . . . . . . . . . . . . . . . . . . .11 8.1Synchronization . . . . . . . . . . . . . . . . . . . . 11 8.2Arbitration . . . . . . . . . . . . . . . . . . . . . . . . . 12 8.3Use of the clock synchronizing
mechanism as a handshake. . . . . . . . . . . 13 9FORMATS WITH 7-BIT ADDRESSES. . . .13 107-BIT ADDRESSING . . . . . . . . . . . . . . . . .15 10.1Definition of bits in the first byte . . . . . . . . 15 10.1.1General call address. . . . . . . . . . . . . . . . . 16 10.1.2START byte . . . . . . . . . . . . . . . . . . . . . . . 17 10.1.3CBUS compatibility. . . . . . . . . . . . . . . . . . 18 11EXTENSIONS TO THE STANDARD-
MODE I2C-BUS SPECIFICATION . . . . . . .19 12FAST-MODE. . . . . . . . . . . . . . . . . . . . . . . .19 13Hs-MODE . . . . . . . . . . . . . . . . . . . . . . . . . .20 13.1High speed transfer. . . . . . . . . . . . . . . . . . 20 13.2Serial data transfer format in Hs-mode. . . 21 13.3Switching from F/S- to Hs-mode and
back . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2313.4Hs-mode devices at lower speed modes. . 24 13.5Mixed speed modes on one serial bus
system. . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 13.5.1F/S-mode transfer in a mixed-speed bus
system. . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 13.5.2Hs-mode transfer in a mixed-speed bus
system. . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 13.5.3Timing requirements for the bridge in a
mixed-speed bus system. . . . . . . . . . . . . . 27 1410-BIT ADDRESSING. . . . . . . . . . . . . . . . 27 14.1Definition of bits in the first two bytes. . . . . 27 14.2Formats with 10-bit addresses. . . . . . . . . . 27 14.3General call address and start byte with
10-bit addressing. . . . . . . . . . . . . . . . . . . . 30 15ELECTRICAL SPECIFICATIONS
AND TIMING FOR I/O STAGES
AND BUS LINES. . . . . . . . . . . . . . . . . . . . 30 15.1Standard- and Fast-mode devices. . . . . . . 30 15.2Hs-mode devices. . . . . . . . . . . . . . . . . . . . 34 16ELECTRICAL CONNECTIONS OF
I2C-BUS DEVICES TO THE BUS LINES . 37 16.1Maximum and minimum values of
resistors R p and R s for Standard-mode
I2C-bus devices . . . . . . . . . . . . . . . . . . . . . 39 17APPLICATION INFORMATION. . . . . . . . . 41 17.1Slope-controlled output stages of
Fast-mode I2C-bus devices. . . . . . . . . . . . 41 17.2Switched pull-up circuit for Fast-mode
I2C-bus devices . . . . . . . . . . . . . . . . . . . . . 41 17.3Wiring pattern of the bus lines. . . . . . . . . . 42 17.4Maximum and minimum values of
resistors R p and R s for Fast-mode
I2C-bus devices . . . . . . . . . . . . . . . . . . . . . 42 17.5Maximum and minimum values of
resistors R p and R s for Hs-mode
I2C-bus devices . . . . . . . . . . . . . . . . . . . . . 42 18BI-DIRECTIONAL LEVEL SHIFTER
FOR F/S-MODE I2C-BUS SYSTEMS . . . . 42 18.1Connecting devices with different
logic levels. . . . . . . . . . . . . . . . . . . . . . . . . 43 18.1.1Operation of the level shifter . . . . . . . . . . . 44 19DEVELOPMENT TOOLS AVAILABLE
FROM PHILIPS. . . . . . . . . . . . . . . . . . . . . 45 20SUPPORT LITERATURE . . . . . . . . . . . . . 46
1PREFACE
1.1Version 1.0 - 1992
This version of the 1992 I2C-bus specification includes the following modifications:
?Programming of a slave address by software has been omitted. The realization of this feature is rather complicated and has not been used.
?The “low-speed mode” has been omitted. This mode is, in fact, a subset of the total I2C-bus specification and need not be specified explicitly.
?The Fast-mode is added. This allows a fourfold increase of the bit rate up to 400kbit/s. Fast-mode devices are downwards compatible i.e. they can be used in a 0 to 100kbit/s I2C-bus system.
?10-bit addressing is added. This allows 1024 additional slave addresses.
?Slope control and input filtering for Fast-mode devices is specified to improve the EMC behaviour.
NOTE: Neither the 100kbit/s I2C-bus system nor the 100kbit/s devices have been changed.
1.2Version
2.0 - 1998
The I2C-bus has become a de facto world standard that is now implemented in over 1000 different ICs and licensed to more than 50 companies. Many of today’s applications, however, require higher bus speeds and lower supply voltages. This updated version of the I2C-bus specification meets those requirements and includes the following modifications:
?The High-speed mode (Hs-mode) is added. This allows an increase in the bit rate up to 3.4Mbit/s. Hs-mode devices can be mixed with Fast- and Standard-mode devices on the one I2C-bus system with bit rates from 0 to 3.4Mbit/s.
?The low output level and hysteresis of devices with a supply voltage of 2V and below has been adapted to meet the required noise margins and to remain compatible with higher supply voltage devices.
?The 0.6V at 6mA requirement for the output stages of Fast-mode devices has been omitted.
?The fixed input levels for new devices are replaced by bus voltage-related levels.
?Application information for bi-directional level shifter is added.
1.3Version
2.1 - 2000
Version 2.1 of the I2C-bus specification includes the following minor modifications:
?After a repeated START condition in Hs-mode, it is possible to stretch the clock signal SCLH (see Section13.2 and Figs22, 25 and 32).
?Some timing parameters in Hs-mode have been relaxed (see Tables6 and 7).
1.4Purchase of Philips I2C-bus components
Purchase of Philips I2C components conveys a license under the Philips’ I2C patent to use the
components in the I2C system provided the system conforms to the I2C specification defined by
Philips.
2THE I2C-BUS BENEFITS DESIGNERS AND MANUFACTURERS
In consumer electronics, telecommunications and industrial electronics, there are often many similarities between seemingly unrelated designs. For example, nearly every system includes:
?Some intelligent control, usually a single-chip microcontroller
?General-purpose circuits like LCD drivers, remote I/O ports, RAM, EEPROM, or data converters
?Application-oriented circuits such as digital tuning and signal processing circuits for radio and video systems, or DTMF generators for telephones with tone dialling.
To exploit these similarities to the benefit of both systems designers and equipment manufacturers, as well as to maximize hardware efficiency and circuit simplicity, Philips developed a simple bi-directional 2-wire bus for efficient inter-IC control. This bus is called the Inter IC or I2C-bus. At present, Philips’ IC range includes more than 150 CMOS and bipolar I2C-bus compatible types for performing functions in all three of the previously mentioned categories. All I2C-bus compatible devices incorporate an on-chip interface which allows them to communicate directly with each other via the I2C-bus. This design concept solves the many interfacing problems encountered when designing digital control circuits.
Here are some of the features of the I2C-bus:
?Only two bus lines are required; a serial data line (SDA) and a serial clock line (SCL)
?Each device connected to the bus is software addressable by a unique address and simple
master/slave relationships exist at all times; masters can operate as master-transmitters or as master-receivers
?It’s a true multi-master bus including collision detection and arbitration to prevent data corruption if two or more masters simultaneously initiate data transfer
?Serial, 8-bit oriented, bi-directional data transfers can be made at up to 100kbit/s in the Standard-mode, up to 400kbit/s in the Fast-mode, or up to 3.4Mbit/s in the High-speed mode
?On-chip filtering rejects spikes on the bus data line to preserve data integrity ?The number of ICs that can be connected to the same bus is limited only by a maximum bus capacitance of 400pF.
Figure1 shows two examples of I2C-bus applications. 2.1Designer benefits
I2C-bus compatible ICs allow a system design to rapidly progress directly from a functional block diagram to a prototype. Moreover, since they ‘clip’ directly onto the
I2C-bus without any additional external interfacing, they allow a prototype system to be modified or upgraded simply by ‘clipping’ or ‘unclipping’ ICs to or from the bus. Here are some of the features of I2C-bus compatible ICs which are particularly attractive to designers:?Functional blocks on the block diagram correspond with the actual ICs; designs proceed rapidly from block diagram to final schematic.
?No need to design bus interfaces because the I2C-bus interface is already integrated on-chip.
?Integrated addressing and data-transfer protocol allow systems to be completely software-defined
?The same IC types can often be used in many different applications
?Design-time reduces as designers quickly become familiar with the frequently used functional blocks represented by I2C-bus compatible ICs
?ICs can be added to or removed from a system without affecting any other circuits on the bus
?Fault diagnosis and debugging are simple; malfunctions can be immediately traced
?Software development time can be reduced by assembling a library of reusable software modules.
In addition to these advantages, the CMOS ICs in the
I2C-bus compatible range offer designers special features which are particularly attractive for portable equipment and battery-backed systems.
They all have:
?Extremely low current consumption
?High noise immunity
?Wide supply voltage range
?Wide operating temperature range.
Fig.1 Two examples of I 2C-bus applications: (a) a high performance highly-integrated TV set
(b) DECT cordless phone base-station.
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SDA SCL
MICRO-CONTROLLER PCB83C528
PLL
SYNTHESIZER
TSA5512
NON-VOLATILE MEMORY PCF8582E
STEREO / DUAL SOUND DECODER TDA9840
HI-FI AUDIO
PROCESSOR TDA9860
SINGLE-CHIP TEXT SAA52XX
M/S COLOUR DECODER TDA9160A
PICTURE SIGNAL
IMPROVEMENT
TDA4670
VIDEO
PROCESSOR
TDA4685
ON-SCREEN
DISPLAY
PCA8510
(a)MSB575
SDA
SCL
LINE
INTERFACE
PCA1070
BURST MODE CONTROLLER
PCD5042
ADPCM
PCD5032
(b)
DTMF
GENERATOR PCD3311
MICRO-CONTROLLER P80CLXXX
2.2Manufacturer benefits
I2C-bus compatible ICs don’t only assist designers, they also give a wide range of benefits to equipment manufacturers because:
?The simple 2-wire serial I2C-bus minimizes interconnections so ICs have fewer pins and there are not so many PCB tracks; result - smaller and less expensive PCBs
?The completely integrated I2C-bus protocol eliminates the need for address decoders and other ‘glue logic’?The multi-master capability of the I2C-bus allows rapid testing and alignment of end-user equipment via external connections to an assembly-line
?The availability of I2C-bus compatible ICs in SO (small outline), VSO (very small outline) as well as DIL packages reduces space requirements even more. These are just some of the benefits. In addition, I2C-bus compatible ICs increase system design flexibility by allowing simple construction of equipment variants and easy upgrading to keep designs up-to-date. In this way, an entire family of equipment can be developed around a basic model. Upgrades for new equipment, or enhanced-feature models (i.e. extended memory, remote control, etc.) can then be produced simply by clipping the appropriate ICs onto the bus. If a larger ROM is needed, it’s simply a matter of selecting a micro-controller with a larger ROM from our comprehensive range. As new ICs supersede older ones, it’s easy to add new features to equipment or to increase its performance by simply unclipping the outdated IC from the bus and clipping on its successor.
3INTRODUCTION TO THE I2C-BUS SPECIFICATION For 8-bit oriented digital control applications, such as those requiring microcontrollers, certain design criteria can be established:
?A complete system usually consists of at least one microcontroller and other peripheral devices such as memories and I/O expanders
?The cost of connecting the various devices within the system must be minimized ?A system that performs a control function doesn’t require high-speed data transfer
?Overall efficiency depends on the devices chosen and the nature of the interconnecting bus structure.
To produce a system to satisfy these criteria, a serial bus structure is needed. Although serial buses don’t have the throughput capability of parallel buses, they do require less wiring and fewer IC connecting pins. However, a bus is not merely an interconnecting wire, it embodies all the formats and procedures for communication within the system.
Devices communicating with each other on a serial bus must have some form of protocol which avoids all possibilities of confusion, data loss and blockage of information. Fast devices must be able to communicate with slow devices. The system must not be dependent on the devices connected to it, otherwise modifications or improvements would be impossible. A procedure has also to be devised to decide which device will be in control of the bus and when. And, if different devices with different clock speeds are connected to the bus, the bus clock source must be defined. All these criteria are involved in the specification of the I2C-bus.
4THE I2C-BUS CONCEPT
The I2C-bus supports any IC fabrication process (NMOS, CMOS, bipolar). Two wires, serial data (SDA) and serial clock (SCL), carry information between the devices connected to the bus. Each device is recognized by a unique address (whether it’s a microcontroller, LCD driver, memory or keyboard interface) and can operate as either a transmitter or receiver, depending on the function of the device. Obviously an LCD driver is only a receiver, whereas a memory can both receive and transmit data. In addition to transmitters and receivers, devices can also be considered as masters or slaves when performing data transfers (see Table 1). A master is the device which initiates a data transfer on the bus and generates the clock signals to permit that transfer. At that time, any device addressed is considered a slave.
Table 1
Definition of I 2C-bus terminology
The I 2C-bus is a multi-master bus. This means that more than one device capable of controlling the bus can be connected to it. As masters are usually micro-controllers, let’s consider the case of a data transfer between two microcontrollers connected to the I 2C-bus (see Fig.2). This highlights the master-slave and receiver-transmitter relationships to be found on the I 2C-bus. It should be noted that these relationships are not permanent, but only
depend on the direction of data transfer at that time. The transfer of data would proceed as follows:
1) Suppose microcontroller A wants to send information to microcontroller B:
?microcontroller A (master), addresses microcontroller B (slave)?microcontroller A (master-transmitter), sends data to microcontroller B (slave- receiver)?microcontroller A terminates the transfer
2) If microcontroller A wants to receive information from microcontroller B:
?microcontroller A (master) addresses microcontroller B (slave)?microcontroller A (master- receiver) receives data from microcontroller B (slave- transmitter)?microcontroller A terminates the transfer.
Even in this case, the master (microcontroller A) generates the timing and terminates the transfer.
The possibility of connecting more than one
microcontroller to the I 2C-bus means that more than one master could try to initiate a data transfer at the same time. To avoid the chaos that might ensue from such an event - an arbitration procedure has been developed. This
procedure relies on the wired-AND connection of all I 2C interfaces to the I 2C-bus.
If two or more masters try to put information onto the bus, the first to produce a ‘one’ when the other produces a ‘zero’ will lose the arbitration. The clock signals during arbitration are a synchronized combination of the clocks generated by the masters using the wired-AND connection to the SCL line (for more detailed information concerning arbitration see Section 8).
TERM DESCRIPTION
T ransmitter The device which sends data to the bus
Receiver The device which receives data from the bus
Master
The device which initiates a transfer, generates clock signals and terminates a transfer
Slave The device addressed by a master Multi-master
More than one master can attempt to control the bus at the same time without corrupting the message Arbitration
Procedure to ensure that, if more than one master simultaneously tries to control the bus, only one is allowed to do so and the winning message is not corrupted
Synchronization
Procedure to synchronize the clock signals of two or more devices
Fig.2 Example of an I 2C-bus configuration using two microcontrollers.
MBC645
SDA SCL
MICRO -CONTROLLER A
STATIC RAM OR EEPROM
LCD DRIVER
GATE ARRAY
ADC
MICRO -CONTROLLER B
Generation of clock signals on the I 2C-bus is always the responsibility of master devices; each master generates its own clock signals when transferring data on the bus. Bus clock signals from a master can only be altered when they are stretched by a slow-slave device holding-down the clock line, or by another master when arbitration occurs.5
GENERAL CHARACTERISTICS
Both SDA and SCL are bi-directional lines, connected to a positive supply voltage via a current-source or pull-up resistor (see Fig.3). When the bus is free, both lines are HIGH. The output stages of devices connected to the bus must have an open-drain or open-collector to perform the wired-AND function. Data on the I 2C-bus can be transferred at rates of up to 100kbit/s in the
Standard-mode, up to 400kbit/s in the Fast-mode, or up to 3.4Mbit/s in the High-speed mode. The number of
interfaces connected to the bus is solely dependent on the bus capacitance limit of 400pF. For information on High-speed mode master devices, see Section 13.
6
BIT TRANSFER
Due to the variety of different technology devices (CMOS, NMOS, bipolar) which can be connected to the I 2C-bus, the levels of the logical ‘0’ (LOW) and ‘1’ (HIGH) are not fixed and depend on the associated level of V DD (see Section 15 for electrical specifications). One clock pulse is generated for each data bit transferred.
6.1
Data validity
The data on the SDA line must be stable during the HIGH period of the clock. The HIGH or LOW state of the data line can only change when the clock signal on the SCL line is LOW (see Fig.4).Fig.3 Connection of Standard- and Fast-mode devices to the I 2C-bus.
MBC631
SCLKN1OUT SCLK IN
SCLK
DATAN1OUT DATA IN DEVICE 1
SDA (Serial Data Line)SCL (Serial Clock Line)
SCLKN2OUT SCLK IN
SCLK DATAN2OUT DATA IN DEVICE 2
V DD
R p
R p
pull-up resistors
Fig.4 Bit transfer on the I 2C-bus.
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MBC621
data line stable;data valid
change of data allowed
SDA
SCL
6.2START and STOP conditions
Within the procedure of the I 2C-bus, unique situations arise which are defined as START (S) and STOP (P) conditions (see Fig.5).
A HIGH to LOW transition on the SDA line while SCL is HIGH is one such unique case. This situation indicates a START condition.
A LOW to HIGH transition on the SDA line while SCL is HIGH defines a STOP condition.
START and STOP conditions are always generated by the master. The bus is considered to be busy after the START condition. The bus is considered to be free again a certain time after the STOP condition. This bus free situation is specified in Section 15.
The bus stays busy if a repeated START (Sr) is generated instead of a STOP condition. In this respect, the START (S) and repeated START (Sr) conditions are functionally identical (see Fig. 10). For the remainder of this document, therefore, the S symbol will be used as a generic term to represent both the START and repeated START conditions, unless Sr is particularly relevant.
Detection of START and STOP conditions by devices connected to the bus is easy if they incorporate the necessary interfacing hardware. However,
microcontrollers with no such interface have to sample the SDA line at least twice per clock period to sense the transition.
Fig.5 START and STOP conditions.
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MBC622
SDA SCL
P
STOP condition
SDA
SCL
S
START condition
7TRANSFERRING DATA 7.1
Byte format
Every byte put on the SDA line must be 8-bits long. The number of bytes that can be transmitted per transfer is unrestricted. Each byte has to be followed by an acknowledge bit. Data is transferred with the most significant bit (MSB) first (see Fig.6). If a slave can’t receive or transmit another complete byte of data until it has performed some other function, for example servicing an internal interrupt, it can hold the clock line SCL LOW to force the master into a wait state. Data transfer then
continues when the slave is ready for another byte of data and releases clock line SCL.
In some cases, it’s permitted to use a different format from the I 2C-bus format (for CBUS compatible devices for example). A message which starts with such an address can be terminated by generation of a STOP condition, even during the transmission of a byte. In this case, no acknowledge is generated (see Section 10.1.3).7.2
Acknowledge
Data transfer with acknowledge is obligatory. The acknowledge-related clock pulse is generated by the master. The transmitter releases the SDA line (HIGH) during the acknowledge clock pulse.
The receiver must pull down the SDA line during the acknowledge clock pulse so that it remains stable LOW
during the HIGH period of this clock pulse (see Fig.7). Of course, set-up and hold times (specified in Section 15) must also be taken into account.
Usually, a receiver which has been addressed is obliged to generate an acknowledge after each byte has been received, except when the message starts with a CBUS address (see Section 10.1.3).
When a slave doesn’t acknowledge the slave address (for example, it’s unable to receive or transmit because it’s performing some real-time function), the data line must be left HIGH by the slave. The master can then generate either a STOP condition to abort the transfer, or a repeated START condition to start a new transfer.
If a slave-receiver does acknowledge the slave address but, some time later in the transfer cannot receive any more data bytes, the master must again abort the transfer. This is indicated by the slave generating the
not-acknowledge on the first byte to follow. The slave leaves the data line HIGH and the master generates a STOP or a repeated START condition.
If a master-receiver is involved in a transfer, it must signal the end of data to the slave- transmitter by not generating an acknowledge on the last byte that was clocked out of the slave. The slave-transmitter must release the data line to allow the master to generate a STOP or repeated START condition.
Fig.6 Data transfer on the I 2C-bus.
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MSC608
Sr or P
SDA
Sr
P
SCL
STOP or repeated START
condition
S or Sr
START or repeated START
condition
12 3 - 89ACK
9ACK
7812MSB
acknowledgement signal from slave
byte complete,interrupt within slave
clock line held low while interrupts are serviced
acknowledgement signal from receiver
Fig.7 Acknowledge on the I 2C-bus.
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MBC602
S START condition
9
821clock pulse for acknowledgement
not acknowledge
acknowledge
DATA OUTPUT BY TRANSMITTER
DATA OUTPUT BY RECEIVER
SCL FROM MASTER
8ARBITRATION AND CLOCK GENERATION 8.1
Synchronization
All masters generate their own clock on the SCL line to transfer messages on the I 2C-bus. Data is only valid during the HIGH period of the clock. A defined clock is therefore needed for the bit-by-bit arbitration procedure to take place.
Clock synchronization is performed using the wired-AND connection of I 2C interfaces to the SCL line. This means
that a HIGH to LOW transition on the SCL line will cause the devices concerned to start counting off their LOW period and, once a device clock has gone LOW, it will hold the SCL line in that state until the clock HIGH state is reached (see Fig.8). However, the LOW to HIGH transition of this clock may not change the state of the SCL line if another clock is still within its LOW period. The SCL line will therefore be held LOW by the device with the longest LOW period. Devices with shorter LOW periods enter a HIGH wait-state during this time.
Fig.8 Clock synchronization during the arbitration procedure.
CLK 1
CLK 2
SCL
counter reset
wait state
start counting HIGH period
MBC632
When all devices concerned have counted off their LOW period, the clock line will be released and go HIGH. There will then be no difference between the device clocks and the state of the SCL line, and all the devices will start counting their HIGH periods. The first device to complete its HIGH period will again pull the SCL line LOW.In this way, a synchronized SCL clock is generated with its LOW period determined by the device with the longest clock LOW period, and its HIGH period determined by the one with the shortest clock HIGH period.8.2
Arbitration
A master may start a transfer only if the bus is free. Two or more masters may generate a START condition within the minimum hold time (t HD;STA ) of the START condition which results in a defined START condition to the bus.
Arbitration takes place on the SDA line, while the SCL line is at the HIGH level, in such a way that the master which transmits a HIGH level, while another master is
transmitting a LOW level will switch off its DATA output stage because the level on the bus doesn’t correspond to its own level.
Arbitration can continue for many bits. Its first stage is comparison of the address bits (addressing information is given in Sections 10 and 14). If the masters are each trying
to address the same device, arbitration continues with comparison of the data-bits if they are master-transmitter, or acknowledge-bits if they are master-receiver. Because address and data information on the I 2C-bus is determined by the winning master, no information is lost during the arbitration process.
A master that loses the arbitration can generate clock pulses until the end of the byte in which it loses the arbitration.
As an Hs-mode master has a unique 8-bit master code, it will always finish the arbitration during the first byte (see Section 13).
If a master also incorporates a slave function and it loses arbitration during the addressing stage, it’s possible that the winning master is trying to address it. The losing
master must therefore switch over immediately to its slave mode.
Figure 9 shows the arbitration procedure for two masters. Of course, more may be involved (depending on how many masters are connected to the bus). The moment there is a difference between the internal data level of the master generating DATA 1 and the actual level on the SDA line, its data output is switched off, which means that a HIGH output level is then connected to the bus. This will not affect the data transfer initiated by the winning master.
Fig.9 Arbitration procedure of two masters.
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MSC609
DATA 1
DATA 2
SDA
SCL
S
master 1 loses arbitration
DATA 1 SDA
Since control of the I 2C-bus is decided solely on the address or master code and data sent by competing masters, there is no central master, nor any order of priority on the bus.
Special attention must be paid if, during a serial transfer, the arbitration procedure is still in progress at the moment when a repeated START condition or a STOP condition is transmitted to the I 2C-bus. If it’s possible for such a situation to occur, the masters involved must send this repeated START condition or STOP condition at the same position in the format frame. In other words, arbitration isn’t allowed between:
?A repeated START condition and a data bit ?A STOP condition and a data bit
?A repeated START condition and a STOP condition.
Slaves are not involved in the arbitration procedure.8.3Use of the clock synchronizing mechanism as a handshake In addition to being used during the arbitration procedure, the clock synchronization mechanism can be used to
enable receivers to cope with fast data transfers, on either a byte level or a bit level.
On the byte level, a device may be able to receive bytes of data at a fast rate, but needs more time to store a received byte or prepare another byte to be transmitted. Slaves can
then hold the SCL line LOW after reception and
acknowledgment of a byte to force the master into a wait state until the slave is ready for the next byte transfer in a type of handshake procedure (see Fig.6).
On the bit level, a device such as a microcontroller with or without limited hardware for the I 2C-bus, can slow down the bus clock by extending each clock LOW period. The speed of any master is thereby adapted to the internal operating rate of this device.
In Hs-mode, this handshake feature can only be used on byte level (see Section 13).9
FORMATS WITH 7-BIT ADDRESSES
Data transfers follow the format shown in Fig.10. After the START condition (S), a slave address is sent. This
address is 7bits long followed by an eighth bit which is a
data direction bit (R/W) - a ‘zero’ indicates a transmission
(WRITE), a ‘one’ indicates a request for data (READ). A
data transfer is always terminated by a STOP condition (P)
generated by the master. However, if a master still wishes
to communicate on the bus, it can generate a repeated START condition (Sr) and address another slave without
first generating a STOP condition. Various combinations of read/write formats are then possible within such a transfer.
Fig.10 A complete data transfer.
handbook, full pagewidth
S 1 – 789 1 – 789 1 – 789
P
STOP condition
START condition
DATA ACK
DATA ACK ADDRESS ACK R/W SDA
SCL
MBC604
Possible data transfer formats are:
?Master-transmitter transmits to slave-receiver. The transfer direction is not changed (see Fig.11).?Master reads slave immediately after first byte (see Fig.12). At the moment of the first acknowledge, the master- transmitter becomes a master- receiver and the slave-receiver becomes a slave-transmitter. This first acknowledge is still generated by the slave. The STOP condition is generated by the master, which has previously sent a not-acknowledge (A).?Combined format (see Fig.13). During a change of direction within a transfer, the START condition and the slave address are both repeated, but with the R/W bit reversed. If a master receiver sends a repeated START condition, it has previously sent a not-acknowledge (A).
NOTES:
https://www.wendangku.net/doc/1218521298.html,bined formats can be used, for example, to
control a serial memory. During the first data byte, the internal memory location has to be written. After the START condition and slave address is repeated, data can be transferred.2.All decisions on auto-increment or decrement of
previously accessed memory locations etc. are taken by the designer of the device.3.Each byte is followed by an acknowledgment bit as
indicated by the A or A blocks in the sequence.4.I 2C-bus compatible devices must reset their bus logic
on receipt of a START or repeated START condition such that they all anticipate the sending of a slave address, even if these START conditions are not positioned according to the proper format.5. A START condition immediately followed by a STOP
condition (void message) is an illegal format.
Fig.11 A master-transmitter addressing a slave receiver with a 7-bit address.
The transfer direction is not changed.
handbook, full pagewidth
,,
,,,,,,,,,,,,MBC605
A/A
A '0' (write)
data transferred
(n bytes + acknowledge)
A = acknowledge (SDA LOW)A = not acknowledge (SDA HIGH)S = START condition P = STOP condition
R/W from master to slave from slave to master
DATA
DATA A SLAVE ADDRESS S P
Fig.12 A master reads a slave immediately after the first byte.
handbook, full pagewidth
,,
,,,,,,,,
MBC606
A
(read)
data transferred (n bytes + acknowledge)
R/W
A
1
P
DATA
DATA
SLAVE ADDRESS
S
A
Fig.13 Combined format.
handbook, full pagewidth
MBC607
DATA A R/W read or write
A/A DATA A R/W (n bytes + ack.)direction of transfer may change at this point.
read or write
(n bytes + ack.)Sr = repeated START condition
A/A *
**not shaded because
transfer direction of
data and acknowledge bits depends on R/W bits.
SLAVE ADDRESS S Sr P
SLAVE ADDRESS 107-BIT ADDRESSING
The addressing procedure for the I 2C-bus is such that the first byte after the START condition usually determines which slave will be selected by the master. The exception is the ‘general call’ address which can address all devices. When this address is used, all devices should, in theory, respond with an acknowledge. However, devices can be made to ignore this address. The second byte of the general call address then defines the action to be taken. This procedure is explained in more detail in
Section 10.1.1. For information on 10-bit addressing, see Section 1410.1
Definition of bits in the first byte
The first seven bits of the first byte make up the slave
address (see Fig.14). The eighth bit is the LSB (least significant bit). It determines the direction of the message. A ‘zero’ in the least significant position of the first byte means that the master will write information to a selected slave. A ‘one’ in this position means that the master will read information from the slave.
When an address is sent, each device in a system
compares the first seven bits after the START condition with its address. If they match, the device considers itself addressed by the master as a slave-receiver or slave-transmitter, depending on the R/W bit.
A slave address can be made-up of a fixed and a programmable part. Since it’s likely that there will be several identical devices in a system, the programmable part of the slave address enables the maximum possible number of such devices to be connected to the I 2C-bus. The number of programmable address bits of a device depends on the number of pins available. For example, if a device has 4 fixed and 3 programmable address bits, a total of 8 identical devices can be connected to the same bus.
The I 2C-bus committee coordinates allocation of I 2C addresses. Further information can be obtained from the Philips representatives listed on the back cover. Two groups of eight addresses (0000XXX and 1111XXX) are reserved for the purposes shown in Table 2. The bit
combination 11110XX of the slave address is reserved for 10-bit addressing (see Section 14).
Fig.14 The first byte after the START procedure.
handbook, halfpage
MBC608
R/W
LSB MSB slave address
Table 2Definition of bits in the first byte
Notes
1. No device is allowed to acknowledge at the reception
of the START byte.
2.The CBUS address has been reserved to enable the
inter-mixing of CBUS compatible and I2C-bus
compatible devices in the same system. I2C-bus
compatible devices are not allowed to respond on
reception of this address.
3.The address reserved for a different bus format is
included to enable I2C and other protocols to be mixed.
Only I2C-bus compatible devices that can work with such formats and protocols are allowed to respond to this address.
10.1.1G ENERAL CALL ADDRESS
The general call address is for addressing every device connected to the I2C-bus. However, if a device doesn’t need any of the data supplied within the general call structure, it can ignore this address by not issuing an acknowledgment. If a device does require data from a general call address, it will acknowledge this address and behave as a slave- receiver. The second and following bytes will be acknowledged by every slave- receiver capable of handling this data. A slave which cannot process one of these bytes must ignore it by
not-acknowledging. The meaning of the general call address is always specified in the second byte (see Fig.15).
There are two cases to consider:
?When the least significant bit B is a ‘zero’.
?When the least significant bit B is a ‘one’.When bit B is a ‘zero’; the second byte has the following definition:
?00000110 (H‘06’). Reset and write programmable part of slave address by hardware. On receiving this 2-byte sequence, all devices designed to respond to the general call address will reset and take in the programmable part of their address. Pre-cautions have to be taken to ensure that a device is not pulling down the SDA or SCL line after applying the supply voltage, since these low levels would block the bus.?00000100 (H‘04’). Write programmable part of slave address by hardware. All devices which define the programmable part of their address by hardware (and which respond to the general call address) will latch this programmable part at the reception of this two byte sequence. The device will not reset.
?00000000 (H‘00’). This code is not allowed to be used as the second byte.
Sequences of programming procedure are published in the appropriate device data sheets.
The remaining codes have not been fixed and devices must ignore them.
When bit B is a ‘one’; the 2-byte sequence is a ‘hardware general call’. This means that the sequence is transmitted by a hardware master device, such as a keyboard scanner, which cannot be programmed to transmit a desired slave address. Since a hardware master doesn’t know in advance to which device the message has to be transferred, it can only generate this hardware general call and its own address - identifying itself to the system (see Fig.16).
The seven bits remaining in the second byte contain the address of the hardware master. This address is recognized by an intelligent device (e.g. a microcontroller) connected to the bus which will then direct the information from the hardware master. If the hardware master can also act as a slave, the slave address is identical to the master address.
SLAVE
ADDRESS
R/W BIT DESCRIPTION 0000 0000General call address 0000 0001ST ART byte(1)
0000 001X CBUS address(2)
0000 010X Reserved for different bus
format(3)
0000 011X Reserved for future purposes 0000 1XX X Hs-mode master code
1111 1XX X Reserved for future purposes 1111 0XX X10-bit slave addressing
Fig.15 General call address format.
MBC623
LSB
second byte
00000000A X X X X X X X B A
first byte
(general call address)
Fig.16 Data transfer from a hardware master-transmitter.
handbook, full pagewidth
MBC624
general call address
(B)
A A second byte
A A (n bytes + ack.)
S 00000000MASTER ADDRESS
1P
DATA DATA In some systems, an alternative could be that the
hardware master transmitter is set in the slave-receiver mode after the system reset. In this way, a system configuring master can tell the hardware master-
transmitter (which is now in slave-receiver mode) to which address data must be sent (see Fig.17). After this
programming procedure, the hardware master remains in the master-transmitter mode.10.1.2
ST ART BYTE
Microcontrollers can be connected to the I 2C-bus in two ways. A microcontroller with an on-chip hardware I 2C-bus interface can be programmed to be only interrupted by requests from the bus. When the device doesn’t have such
an interface, it must constantly monitor the bus via
software. Obviously, the more times the microcontroller monitors, or polls the bus, the less time it can spend carrying out its intended function.
There is therefore a speed difference between fast hardware devices and a relatively slow microcontroller which relies on software polling.
In this case, data transfer can be preceded by a start procedure which is much longer than normal (see Fig.18). The start procedure consists of:?A START condition (S)?A START byte (00000001)?An acknowledge clock pulse (ACK)?A repeated START condition (Sr).
Fig.17 Data transfer by a hardware-transmitter capable of dumping data directly to slave devices. (a) Configuring master sends dump address to hardware master
(b) Hardware master dumps data to selected slave.
handbook, full pagewidth
,,,,,,,,,
,,,,,,
,,,,,,,,,,,,MBC609
write
A
A (a)
(b)
R/W write
A A (n bytes + ack.)
A/A
R/W S P
SLAVE ADDR. H/W MASTER DUMP ADDR. FOR H/W MASTER X S
P
DUMP ADDR. FROM H/W MASTER DATA DATA
Fig.18 START byte procedure.MBC633
S
9
8
2
1
Sr
7
ACK
dummy
acknowledge
(HIGH)
start byte 00000001
SDA SCL
After the START condition S has been transmitted by a master which requires bus access, the START byte (00000001) is transmitted. Another microcontroller can therefore sample the SDA line at a low sampling rate until one of the seven zeros in the START byte is detected. After detection of this LOW level on the SDA line, the microcontroller can switch to a higher sampling rate to find the repeated START condition Sr which is then used for synchronization.
A hardware receiver will reset on receipt of the repeated START condition Sr and will therefore ignore the START byte.
An acknowledge-related clock pulse is generated after the START byte. This is present only to conform with the byte handling format used on the bus. No device is allowed to acknowledge the START byte.10.1.3CBUS COMPATIBILITY
CBUS receivers can be connected to the Standard-mode I2C-bus. However, a third bus line called DLEN must then be connected and the acknowledge bit omitted. Normally, I2C transmissions are sequences of 8-bit bytes; CBUS compatible devices have different formats.
In a mixed bus structure, I2C-bus devices must not respond to the CBUS message. For this reason, a special CBUS address (0000001X) to which no I2C-bus compatible device will respond, has been reserved. After transmission of the CBUS address, the DLEN line can be made active and a CBUS-format transmission sent (see Fig.19). After the STOP condition, all devices are again ready to accept data.
Master-transmitters can send CBUS formats after sending the CBUS address. The transmission is ended by a STOP condition, recognized by all devices.
NOTE: If the CBUS configuration is known, and expansion with CBUS compatible devices isn’t foreseen, the designer is allowed to adapt the hold time to the specific requirements of the device(s) used.
MBC634
S P STOP condition
CBUS load pulse
n - data bits
CBUS address
START condition
R/W bit
ACK related clock pulse
SDA
SCL
DLEN
Fig.19 Data format of transmissions with CBUS transmitter/receiver.
11EXTENSIONS TO THE STANDARD-MODE I 2C-BUS
SPECIFICATION The Standard-mode I 2C-bus specification, with its data transfer rate of up to 100kbit/s and 7-bit addressing, has been in existence since the beginning of the 1980’s. This concept rapidly grew in popularity and is today accepted worldwide as a de facto standard with several hundred different compatible ICs on offer from Philips
Semiconductors and other suppliers. To meet the
demands for higher speeds, as well as make available more slave address for the growing number of new devices, the Standard-mode I 2C-bus specification was upgraded over the years and today is available with the following extensions:
? Fast-mode , with a bit rate up to 400kbit/s.
? High-speed mode (Hs-mode), with a bit rate up to 3.4Mbit/s.?10-bit addressing , which allows the use of up to 1024 additional slave addresses.There are two main reasons for extending the regular I 2C-bus specification:
?Many of today’s applications need to transfer large amounts of serial data and require bit rates far in excess of 100kbit/s (Standard-mode), or even 400kbit/s
(Fast-mode). As a result of continuing improvements in semiconductor technologies, I 2C-bus devices are now available with bit rates of up to 3.4Mbit/s (Hs-mode) without any noticeable increases in the manufacturing cost of the interface circuitry.?As most of the 112addresses available with the 7-bit addressing scheme were soon allocated, it became apparent that more address combinations were required to prevent problems with the allocation of slave
addresses for new devices. This problem was resolved with the new 10-bit addressing scheme, which allowed about a tenfold increase in available addresses.New slave devices with a Fast- or Hs-mode I 2C-bus interface can have a 7- or a 10-bit slave address. If
possible, a 7-bit address is preferred as it is the cheapest hardware solution and results in the shortest message length. Devices with 7- and 10-bit addresses can be mixed in the same I 2C-bus system regardless of whether it is an F/S- or Hs-mode system. Both existing and future masters can generate either 7- or 10-bit addresses.12FAST -MODE
With the Fast-mode I 2C-bus specification, the protocol, format, logic levels and maximum capacitive load for the SDA and SCL lines quoted in the Standard-mode I 2C-bus specification are unchanged. New devices with an I 2C-bus interface must meet at least the minimum requirements of the Fast- or Hs-mode specification (see Section 13).Fast-mode devices can receive and transmit at up to 400kbit/s. The minimum requirement is that they can synchronize with a 400kbit/s transfer; they can then
prolong the LOW period of the SCL signal to slow down the transfer. Fast-mode devices are downward-compatible and can communicate with Standard-mode devices in a 0to 100kbit/s I 2C-bus system. As Standard-mode
devices, however, are not upward compatible, they should not be incorporated in a Fast-mode I 2C-bus system as they cannot follow the higher transfer rate and unpredictable states would occur.
The Fast-mode I2C-bus specification has the following additional features compared with the Standard-mode:?The maximum bit rate is increased to 400kbit/s.?Timing of the serial data (SDA) and serial clock (SCL) signals has been adapted. There is no need for compatibility with other bus systems such as CBUS because they cannot operate at the increased bit rate.?The inputs of Fast-mode devices incorporate spike suppression and a Schmitt trigger at the SDA and SCL inputs.
?The output buffers of Fast-mode devices incorporate slope control of the falling edges of the SDA and SCL signals.
?If the power supply to a Fast-mode device is switched off, the SDA and SCL I/O pins must be floating so that they don’t obstruct the bus lines.
?The external pull-up devices connected to the bus lines must be adapted to accommodate the shorter maximum permissible rise time for the Fast-mode I2C-bus. For bus loads up to 200pF, the pull-up device for each bus line can be a resistor; for bus loads between 200pF and 400pF, the pull-up device can be a current source
(3mA max.) or a switched resistor circuit (see Fig.43).
13Hs-MODE
High-speed mode (Hs-mode) devices offer a quantum leap in I2C-bus transfer speeds. Hs-mode devices can transfer information at bit rates of up to 3.4Mbit/s, yet they remain fully downward compatible with Fast- or Standard-mode (F/S-mode) devices for bi-directional communication in a mixed-speed bus system. With the exception that arbitration and clock synchronization is not performed during the Hs-mode transfer, the same serial bus protocol and data format is maintained as with the
F/S-mode system. Depending on the application, new devices may have a Fast or Hs-mode I2C-bus interface, although Hs-mode devices are preferred as they can be designed-in to a greater number of applications.
13.1High speed transfer
To achieve a bit transfer of up to 3.4Mbit/s the following improvements have been made to the regular I2C-bus specification:
?Hs-mode master devices have an open-drain output buffer for the SDAH signal and a combination of an open-drain pull-down and current-source pull-up circuit on the SCLH output(1). This current-source circuit shortens the rise time of the SCLH signal. Only the
current-source of one master is enabled at any one time, and only during Hs-mode.
?No arbitration or clock synchronization is performed during Hs-mode transfer in multi-master systems, which speeds-up bit handling capabilities. The arbitration procedure always finishes after a preceding master code transmission in F/S-mode.
?Hs-mode master devices generate a serial clock signal with a HIGH to LOW ratio of 1 to 2. This relieves the timing requirements for set-up and hold times.
?As an option, Hs-mode master devices can have a built-in bridge(1). During Hs-mode transfer, the high speed data (SDAH) and high-speed serial clock (SCLH) lines of Hs-mode devices are separated by this bridge from the SDA and SCL lines of F/S-mode devices. This reduces the capacitive load of the SDAH and SCLH lines resulting in faster rise and fall times.
?The only difference between Hs-mode slave devices and F/S-mode slave devices is the speed at which they operate. Hs-mode slaves have open-drain output buffers on the SCLH and SDAH outputs. Optional pull-down transistors on the SCLH pin can be used to stretch the LOW level of the SCLH signal, although this is only allowed after the acknowledge bit in Hs-mode transfers.?The inputs of Hs-mode devices incorporate spike suppression and a Schmitt trigger at the SDAH and SCLH inputs.
?The output buffers of Hs-mode devices incorporate slope control of the falling edges of the SDAH and SCLH signals.
Figure20 shows the physical I2C-bus configuration in a system with only Hs-mode devices. Pins SDA and SCL on the master devices are only used in mixed-speed bus systems and are not connected in an Hs-mode only system. In such cases, these pins can be used for other functions.
Optional series resistors R s protect the I/O stages of the I2C-bus devices from high-voltage spikes on the bus lines and minimize ringing and interference.
Pull-up resistors R p maintain the SDAH and SCLH lines at a HIGH level when the bus is free and ensure the signals are pulled up from a LOW to a HIGH level within the required rise time. For higher capacitive bus-line loads (>100pF), the resistor R p can be replaced by external current source pull-ups to meet the rise time requirements. Unless proceeded by an acknowledge bit, the rise time of the SCLH clock pulses in Hs-mode transfers is shortened by the internal current-source pull-up circuit MCS of the active master.
(1)Patent application pending.
i2c协议以及其相关bug分析总结
i2c协议以及其相关bug分析总结 篇一：I2C协议以及其相关bug分析总结_袁刚20XX1202 一、I2C通信协议 ................................................ ................................................... (2) 1、I2C 协议：............................................... . (2) 2、I2C时序 ................................................ . (3) 3、I2C协议中文版本 ................................................ .. (7) 二、I2C协议中遇到的BUG分析 ................................................ .. (8) 1、项目A72A中时序问题 ................................................ (8)
2、T03 Light sensor 无ACK问题................................................. (8) 3、S26I 电池以及F01电池问题................................................. (9) 4、现象ACK后面的半高的小毛刺分析 ................................................ (10) 5、T05C G-sensor无数据问题 ................................................ .. (11) 三、I2C协议使用注意事项 ................................................ .. (12) 1、I2C level shift 普通MOS以及level shift IC (12) 2、I2C使用注意事项以及bug总结 ................................................ (15) 文档整理人：袁刚 20XX年12月2日 一、I2C通信协议
I2C总线协议详解
I2C总线协议详解 I2C总线定义 -------------------------------------------------------------------------------- I2C(Inter－Integrated Circuit)总线是一种由PHILIPS公司开发的两线式串行总线，用于连接微控制器及其外围设备。I2C总线产生于在80年代，最初为音频和视频设备开发，如今主要在服务器管理中使用，其中包括单个组件状态的通信。例如管理员可对各个组件进行查询，以管理系统的配置或掌握组件的功能状态，如电源和系统风扇。可随时监控内存、硬盘、网络、系统温度等多个参数，增加了系统的安全性，方便了管理。 I2C总线特点 -------------------------------------------------------------------------------- I2C总线最主要的优点是其简单性和有效性。由于接口直接在组件之上，因此I2C总线占用的空间非常小，减少了电路板的空间和芯片管脚的数量，降低了互联成本。总线的长度可高达25英尺，并且能够以10Kbps的最大传输速率支持40个组件。I2C总线的另一个优点是，它支持多主控(multimastering)，其中任何能够进行发送和接收的设备都可以成为主总线。一个主控能够控制信号的传输和时钟频率。当然，在任何时间点上只能有一个主控。 I2C总线工作原理 -------------------------------------------------------------------------------- 总线的构成及信号类型 -------------------------------------------------------------------------------- I2C总线是由数据线SDA和时钟SCL构成的串行总线，可发送和接收数据。在CPU与被控IC之间、IC与IC之间进行双向传送，最高传送速率100kbps。各种被控制电路均并联在这条总线上，但就像电话机一样只有拨通各自的号码才能工作，所以每个电路和模块都有唯一的地址，在信息的传输过程中，I2C总线上并接的每一模块电路既是主控器（或被控器），又是发送器（或接收器），这取决于它所要完成的功能。CPU发出的控制信号分为地址码和控制量两部分，地址码用来选址，即接通需要控制的电路，确定控制的种类；控制量决定该调整的类别（如对比度、亮度等）及需要调整的量。这样，各控制电路虽然挂在同一条总线上，却彼此独立，互不相关。 I2C总线在传送数据过程中共有三种类型信号，它们分别是：开始信号、结束信号和应答信号。 开始信号：SCL为高电平时，SDA由高电平向低电平跳变，开始传送数据。 结束信号：SCL为高电平时，SDA由低电平向高电平跳变，结束传送数据。
简单的I2C协议理解 i2c程序(调试通过)
简单的I2C协议理解 一. 技术性能: 工作速率有100K和400K两种； 支持多机通讯； 支持多主控模块，但同一时刻只允许有一个主控； 由数据线SDA和时钟SCL构成的串行总线； 每个电路和模块都有唯一的地址； 每个器件可以使用独立电源 二. 基本工作原理: 以启动信号START来掌管总线，以停止信号STOP来释放总线； 每次通讯以START开始，以STOP结束； 启动信号START后紧接着发送一个地址字节，其中7位为被控器件的地址码，一位为读/写控制位R/W,R /W位为0表示由主控向被控器件写数据，R/W为1表示由主控向被控器件读数据； 当被控器件检测到收到的地址与自己的地址相同时，在第9个时钟期间反馈应答信号； 每个数据字节在传送时都是高位(MSB)在前； 写通讯过程: 1. 主控在检测到总线空闲的状况下，首先发送一个START信号掌管总线； 2. 发送一个地址字节(包括7位地址码和一位R/W)； 3. 当被控器件检测到主控发送的地址与自己的地址相同时发送一个应答信号(ACK)； 4. 主控收到ACK后开始发送第一个数据字节； 5. 被控器收到数据字节后发送一个ACK表示继续传送数据，发送NACK表示传送数据结束； 6. 主控发送完全部数据后，发送一个停止位STOP，结束整个通讯并且释放总线； 读通讯过程: 1. 主控在检测到总线空闲的状况下，首先发送一个START信号掌管总线； 2. 发送一个地址字节(包括7位地址码和一位R/W)； 3. 当被控器件检测到主控发送的地址与自己的地址相同时发送一个应答信
号(ACK)； 4. 主控收到ACK后释放数据总线，开始接收第一个数据字节； 5. 主控收到数据后发送ACK表示继续传送数据，发送NACK表示传送数据结束； 6. 主控发送完全部数据后，发送一个停止位STOP，结束整个通讯并且释放总线； 四. 总线信号时序分析 1. 总线空闲状态 SDA和SCL两条信号线都处于高电平，即总线上所有的器件都释放总线，两条信号线各自的上拉电阻把电平拉高； 2. 启动信号START 时钟信号SCL保持高电平，数据信号SDA的电平被拉低(即负跳变)。启动信号必须是跳变信号，而且在建立该信号前必修保证总线处于空闲状态； 3. 停止信号STOP 时钟信号SCL保持高电平，数据线被释放，使得SDA返回高电平(即正跳变)，停止信号也必须是跳变信号。 4. 数据传送 SCL线呈现高电平期间，SDA线上的电平必须保持稳定，低电平表示0(此时的线电压为地电压)，高电平表示1(此时的电压由元器件的VDD决定)。只有在SCL线为低电平期间，SDA上的电平允许变化。 5. 应答信号ACK I2C总线的数据都是以字节(8位)的方式传送的，发送器件每发送一个字节之后，在时钟的第9个脉冲期间释放数据总线，由接收器发送一个ACK(把数据总线的电平拉低)来表示数据成功接收。 6. 无应答信号NACK 在时钟的第9个脉冲期间发送器释放数据总线，接收器不拉低数据总线表示一个NACK，NACK有两种用途: a. 一般表示接收器未成功接收数据字节； b. 当接收器是主控器时，它收到最后一个字节后，应发送一个NACK信号，以通知被控发送器结束数据发送，并释放总线，以便主控接收器发送一个停止信号STOP。 五. 寻址约定
I2C总线协议规范 v2.1
THE I2C-BUS SPECIFICATION VERSION 2.1 JANUARY 2000
CONTENTS 1PREFACE. . . . . . . . . . . . . . . . . . . . . . . . . . .3 1.1Version 1.0 - 1992. . . . . . . . . . . . . . . . . . . . 3 1.2Version 2.0 - 198. . . . . . . . . . . . . . . . . . . . . 3 1.3Version 2.1 - 1999. . . . . . . . . . . . . . . . . . . . 3 1.4Purchase of Philips I2C-bus components . . 3 2THE I2C-BUS BENEFITS DESIGNERS AND MANUFACTURERS. . . . . . . . . . . . . . .4 2.1Designer benefits . . . . . . . . . . . . . . . . . . . . 4 2.2Manufacturer benefits. . . . . . . . . . . . . . . . . 6 3INTRODUCTION TO THE I2C-BUS SPECIFICATION . . . . . . . . . . . . . . . . . . . . .6 4THE I2C-BUS CONCEPT . . . . . . . . . . . . . . .6 5GENERAL CHARACTERISTICS . . . . . . . . .8 6BIT TRANSFER . . . . . . . . . . . . . . . . . . . . . .8 6.1Data validity . . . . . . . . . . . . . . . . . . . . . . . . 8 6.2START and STOP conditions. . . . . . . . . . . 9 7TRANSFERRING DATA. . . . . . . . . . . . . . .10 7.1Byte format . . . . . . . . . . . . . . . . . . . . . . . . 10 7.2Acknowledge. . . . . . . . . . . . . . . . . . . . . . . 10 8ARBITRATION AND CLOCK GENERATION . . . . . . . . . . . . . . . . . . . . . .11 8.1Synchronization . . . . . . . . . . . . . . . . . . . . 11 8.2Arbitration . . . . . . . . . . . . . . . . . . . . . . . . . 12 8.3Use of the clock synchronizing mechanism as a handshake. . . . . . . . . . . 13 9FORMATS WITH 7-BIT ADDRESSES. . . .13 107-BIT ADDRESSING . . . . . . . . . . . . . . . . .15 10.1Definition of bits in the first byte . . . . . . . . 15 10.1.1General call address. . . . . . . . . . . . . . . . . 16 10.1.2START byte . . . . . . . . . . . . . . . . . . . . . . . 17 10.1.3CBUS compatibility. . . . . . . . . . . . . . . . . . 18 11EXTENSIONS TO THE STANDARD- MODE I2C-BUS SPECIFICATION . . . . . . .19 12FAST-MODE. . . . . . . . . . . . . . . . . . . . . . . .19 13Hs-MODE . . . . . . . . . . . . . . . . . . . . . . . . . .20 13.1High speed transfer. . . . . . . . . . . . . . . . . . 20 13.2Serial data transfer format in Hs-mode. . . 21 13.3Switching from F/S- to Hs-mode and back . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2313.4Hs-mode devices at lower speed modes. . 24 13.5Mixed speed modes on one serial bus system. . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 13.5.1F/S-mode transfer in a mixed-speed bus system. . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 13.5.2Hs-mode transfer in a mixed-speed bus system. . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 13.5.3Timing requirements for the bridge in a mixed-speed bus system. . . . . . . . . . . . . . 27 1410-BIT ADDRESSING. . . . . . . . . . . . . . . . 27 14.1Definition of bits in the first two bytes. . . . . 27 14.2Formats with 10-bit addresses. . . . . . . . . . 27 14.3General call address and start byte with 10-bit addressing. . . . . . . . . . . . . . . . . . . . 30 15ELECTRICAL SPECIFICATIONS AND TIMING FOR I/O STAGES AND BUS LINES. . . . . . . . . . . . . . . . . . . . 30 15.1Standard- and Fast-mode devices. . . . . . . 30 15.2Hs-mode devices. . . . . . . . . . . . . . . . . . . . 34 16ELECTRICAL CONNECTIONS OF I2C-BUS DEVICES TO THE BUS LINES . 37 16.1Maximum and minimum values of resistors R p and R s for Standard-mode I2C-bus devices . . . . . . . . . . . . . . . . . . . . . 39 17APPLICATION INFORMATION. . . . . . . . . 41 17.1Slope-controlled output stages of Fast-mode I2C-bus devices. . . . . . . . . . . . 41 17.2Switched pull-up circuit for Fast-mode I2C-bus devices . . . . . . . . . . . . . . . . . . . . . 41 17.3Wiring pattern of the bus lines. . . . . . . . . . 42 17.4Maximum and minimum values of resistors R p and R s for Fast-mode I2C-bus devices . . . . . . . . . . . . . . . . . . . . . 42 17.5Maximum and minimum values of resistors R p and R s for Hs-mode I2C-bus devices . . . . . . . . . . . . . . . . . . . . . 42 18BI-DIRECTIONAL LEVEL SHIFTER FOR F/S-MODE I2C-BUS SYSTEMS . . . . 42 18.1Connecting devices with different logic levels. . . . . . . . . . . . . . . . . . . . . . . . . 43 18.1.1Operation of the level shifter . . . . . . . . . . . 44 19DEVELOPMENT TOOLS AVAILABLE FROM PHILIPS. . . . . . . . . . . . . . . . . . . . . 45 20SUPPORT LITERATURE . . . . . . . . . . . . . 46
i方c总线协议
竭诚为您提供优质文档/双击可除 i方c总线协议 篇一：i2c总线协议 1.i2c协议 2条双向串行线，一条数据线sda，一条时钟线scl。 sda传输数据是大端传输，每次传输8bit，即一字节。 支持多主控(multimastering)，任何时间点只能有一个主控。 总线上每个设备都有自己的一个addr，共7个bit，广播地址全0. 系统中可能有多个同种芯片，为此addr分为固定部分和可编程部份，细节视芯片而定，看datasheet。 1.1i2c位传输 数据传输：scl为高电平时，sda线若保持稳定，那么sda上是在传输数据bit； 若sda发生跳变，则用来表示一个会话的开始或结束（后面讲）数据改变：scl为低电平时，sda线才能改变传输的bit 1.2i2c开始和结束信号
开始信号：scl为高电平时，sda由高电平向低电平跳变，开始传送数据。结束信号：scl为高电平时，sda由低电平向高电平跳变，结束传送数据。 1.3i2c应答信号 master每发送完8bit数据后等待slave的ack。 即在第9个clock，若从ic发ack，sda会被拉低。 若没有ack，sda会被置高，这会引起master发生RestaRt或stop流程，如下所示： 1.4i2c写流程 写寄存器的标准流程为： 1.master发起staRt 2.master发送i2caddr（7bit）和w操作0（1bit），等待ack 3.slave发送ack 4.master发送regaddr（8bit），等待ack 5.slave发送ack 6.master发送data（8bit），即要写入寄存器中的数据，等待ack 7.slave发送ack 8.第6步和第7步可以重复多次，即顺序写多个寄存器 9.master发起stop 写一个寄存器
I2c总线协议
1.I2C协议 2条双向串行线，一条数据线SDA，一条时钟线SCL。 SDA传输数据是大端传输，每次传输8bit，即一字节。 支持多主控(multimastering)，任何时间点只能有一个主控。 总线上每个设备都有自己的一个addr，共7个bit，广播地址全0. 系统中可能有多个同种芯片，为此addr分为固定部分和可编程部份，细节视芯片而定，看datasheet。 1.1 I2C位传输 数据传输：SCL为高电平时，SDA线若保持稳定，那么SDA上是在传输数据bit； 若SDA发生跳变，则用来表示一个会话的开始或结束（后面讲） 数据改变：SCL为低电平时，SDA线才能改变传输的bit 1.2 I2C开始和结束信号 开始信号：SCL为高电平时，SDA由高电平向低电平跳变，开始传送数据。结束信号：SCL为高电平时，SDA由低电平向高电平跳变，结束传送数据。
1.3 I2C应答信号 Master每发送完8bit数据后等待Slave的ACK。 即在第9个clock，若从IC发ACK，SDA会被拉低。 若没有ACK，SDA会被置高，这会引起Master发生RESTART或STOP流程，如下所示： 1.4 I2C写流程 写寄存器的标准流程为： 1. Master发起START 2. Master发送I2C addr（7bit）和w操作0（1bit），等待ACK 3. Slave发送ACK 4. Master发送regaddr（8bit），等待ACK 5. Slave发送ACK 6. Master发送data（8bit），即要写入寄存器中的数据，等待ACK 7. Slave发送ACK 8. 第6步和第7步可以重复多次，即顺序写多个寄存器
I2C总线协议及工作原理
I2C总线协议及工作原理 一、概述 1、I2C总线只有两根双向信号线。一根是数据线SDA，另一根是时钟线SCL。 SCL：上升沿将数据输入到每个EEPROM器件中；下降沿驱动EEPROM器件输出数据。(边沿触发) SDA：双向数据线，为OD门，与其它任意数量的OD与OC门成"线与"关系。 I2C总线通过上拉电阻接正电源。当总线空闲时，两根线均为高电平（SDL=1;SCL=1）。连到总线上的任一器件输出的低电平，都将使总线的信号变低，即各器件的SDA及SCL都是线“与”关系。 2、主设备与从设备 系统中的所有外围器件都具有一个7位的"从器件专用地址码"，其中高4位为器件类型，由生产厂家制定，低3位为器件引脚定义地址，由使用者定义。主控器件通过地址码建立多机通信的机制，因此I2C总线省去了外围器件的片选线，这样无论总线上挂接多少个器件，其系统仍然为简约的二线结构。终端挂载在总线上，有主端和从端之分，主端必须是带有CPU的逻辑模块，在同一总线上同一时刻使能有一个主端，可以有多个从端，从端的数量受地址空间和总线的最大电容400pF的限制。 主端主要用来驱动SCL line； 从设备对主设备产生响应； 二者都可以传输数据，但是从设备不能发起传输，且传输是受到主设备控制的。 二、协议 1.空闲状态 I2C总线总线的SDA和SCL两条信号线同时处于高电平时，规定为总线的空闲状态。此时各个器件的输出级场效应管均处在截止状态，即释放总线，由两条信号线各自的上拉电阻把电平拉高。 2.起始位与停止位的定义： 起始信号：当SCL为高期间，SDA由高到低的跳变；启动信号是一种电平跳变时序信号，而不是一个电平信号。 停止信号：当SCL为高期间，SDA由低到高的跳变；停止信号也是一种电平跳变时序信号，而不是一个电平信号。 起始和终止信号都是由主机发出的，在起始信号产生后，总线就处于被占用的状态；在终止信号产生后，总线就处于空闲状态。
I2C总线协议程序
C程序代码]I2C总线协议程序 程序代码 2009-10-11 14:05 阅读48 评论0 /**************************************************************** I2C总线协议程序 ****************************************************************/ #define NOP {_nop_();_nop_();_nop_();_nop_();} sbit SDA=P1^2; /*模拟I2C数据传送位*/ sbit SCL=P1^3; /*模拟I2C时钟控制位*/ bit ack; /*应答标志位*/ void Start_I2c() { SDA=1; NOP; SCL=1; NOP; SDA=0; NOP; SCL=0; NOP; } void Stop_I2c() { SDA=0; NOP;
SCL=1; NOP; SDA=1; NOP; } void Senduchar(uchar c) { uchar i; for(i=0;i<8;i++) { c<<=1; SDA=CY; NOP; SCL=1; NOP; SCL=0; NOP; } SDA=1; NOP; SCL=1; NOP; if(SDA==1) ack=0; else ack=1; SCL=0; NOP; } uchar Rcvuchar() {
uchar i,x=0; SDA=1; for(i=0;i<8;i++) { SCL=0; NOP; SCL=1; NOP; x=x<<1; if(SDA) x=x+1; NOP; } SCL=0; NOP; return(x); } void Ack_I2c(bit a) { SDA=a; NOP; SCL=1; NOP; SCL=0; NOP; } bit ISendStr(uchar sla,uchar suba,uchar *s,uchar no) { uchar i;
SPI、I2C、UART、USB串行总线协议的区别
SPI、I2C、UART、USB串行总线协议的区别 SPI、I2C、UART三种串行总线协议的区别 第一个区别当然是名字： SPI(Serial Peripheral Interface：串行外设接口); I2C(INTER IC BUS) UART(Universal Asynchronous Receiver Transmitter：通用异步收发器) 第二，区别在电气信号线上： SPI总线由三条信号线组成：串行时钟(SCLK)、串行数据输出( SDO)、串行数据输入(SDI)。SPI总线可以实现多个SPI 设备互 相连接。提供SPI串行时钟的SPI设备为SPI主机或主设备(Mast er)，其他设备为SPI从机或从设备(Slave)。主从设备间可 以 实现全双工通信，当有多个从设备时，还可以增加一条从设备 选择线。 如果用通用IO口模拟SPI总线，必须要有一个输出口(SDO)，一
个输入口(SDI)，另一个口则视实现的设备类型而定，如果要实现主从设备，则需输入输出口，若只实现主设备，则需输出 口即可，若只实现从设备，则只需输入口即可。 I2C总线是双向、两线(SCL、SDA)、串行、多主控（multi-mas ter）接口标准，具有总线仲裁机制，非常适合在器件之间进行近距离、非经常性的数据通信。在它的协议体系中，传输数 据时都会带上目的设备的设备地址，因此可以实现设备组网。如果用通用IO口模拟I2C总线，并实现双向传输，则需一 个输 入输出口(SDA)，另外还需一个输出口(SCL)。（注：I2C资 料 了解得比较少，这里的描述可能很不完备） UART总线是异步串口，因此一般比前两种同步串口的结构要复 杂很多，一般由波特率产生器(产生的波特率等于传输波特率的16倍)、UART接收器、UART发送器组成，硬件上由两根线， 一根用于发送，一根用于接收。 显然，如果用通用IO口模拟UART总线，则需一个输入口，一个
I2C协议简介
I2C协议规范 一．I2C协议 I2C协议是有PHILIPS公司在1992年最先提出，乃PHILIPS公司专利。只要购买Philips的I2C元件同时传递了一个在Philips的I2C专利下，在I2C系统 使用元件使系统符合由Philips定义的I2C规范的许可证。任何使用I2C的元件 都必须得到PHILIPS公司的授权。 二．I2C总线的特征 1．只要求两条总线线路一条串行数据线（SDA）一条串行时钟线（SCL）。 同时SDL和SCL都是双向线路，分别通过上拉电阻连接到正的电源电压。 2.每个连接到总线的器件都可以通过唯一的地址和一直存在的简单的主 机/从机关系软件设定地址;主机可以作为主机发送器或主机接收器。 3.它是一个真正的多主机总线，如果两个或更多主机同时初始化数据传输 可以通过冲突检测和仲裁防止数据被破坏。 4.串行的8位双向数据传输位速率在标准模式下可达100kbit/s。快速模 式下可达400kbit/s。高速模式下可达3.4Mbit/s。 5.片上的滤波器可以滤去总线数据线上的毛刺波，保证数据完整。 6.连接到相同总线的IC数量只受到总线的最大电容400pF限制。 三．I2C总线的概念 I2C两线――串行数据SDA和串行时钟SCL线在连接到总线的器件间传递信息。每个器件都有一个唯一的地址识别。无论是微控制器，LCD 驱动器，存储器或键盘接口，都可以作为一个发送器或接收器，由器件的 功能决定。很明显LCD驱动器只是一个接收器，而存储器则既可以接收又 可以发送数据。除了发送器和接收器外，器件在执行数据传输时也可以被 看作是主机或从机。主机是初始化总线的数据传输并产生允许传输的时钟 信号的器件。此时任何被寻址的器件都被认为是从机。在I2C总线上，无 论主机是接受方还是发送方，时钟信号永远是主机控制。 四．总线数据有效性 SDA线上的数据必须在时钟的高电平周期保持稳定。数据线的高或低电平状态只有在SCL线的时钟信号是低电平时才能改变。 五．起始和停止条件 在I2C总线中，唯一出现SCL高电平SDA电平变化的是被定义为起始S和停止P的情况。其中一种情况是在SCL线是高电平时SDA线从高 电平向低电平切换，这个情况表示起始条件。当SCL是高电平时SDA线 由低电平向高电平切换，表示停止条件。
I2c总线协议
编号：_ ______________ 本资料为word版本，可以直接编辑和打印，感谢您的下载 I2c总线协议 甲方：___________________ 乙方：___________________ 日期：___________________
2条双向申行线，一条数据线，一条时钟线。 传输数据是大端传输，每次传输8 ,即一字节。 支持多主控（）,任何时间点只能有一个主控。 总线上每个设备都有自己的一个，共7个，广播地址全0. 系统中可能有多个同种芯片，为此分为固定部分和可编程部份, 定，看。 细节视芯片而1.1 I2C 位传输 数据传输：为高电平时，线若保持稳定，那么上是在传输数据； 若发生跳变，则用来表示一个会话的开始或结束（后面讲） 数据改变：为低电平■时，线才能改变传输的 皿 /〔i~~%一 I -\ y \— L—_ 数据有效I改变数据I 1, 1 1.2 I2C开始和结束信号 开始信号：为高电平时，由高电平向低电平跳变，开始传送数据 结束信号：为高电平■时，由低电平■向高电平跳变，结束传送数据
1.3 I2C 应答信号 每发送完8数据后等待的。 即在第9个，若从发，会被拉低。 若没有，会被置高，这会引起发生或流程，如下所示： I I SCL ~「 代国*；.无同：耳m 何何 代凤国同何同伉m 何二 SDA^同两寂两回祚城.寂网环T 回m 回同函D7]，\__j~ [ -------------------------------------- Galling address START I 1.4 I2C 写流程 写寄存器的标准流程为： 1. 发起 2. 发送I2C (7)和w 操作0 (1),等待 3. 发送 4. 发送(8),等待 5. 发送 6. 发送(8),即要写入寄存器中的数据，等待 7. 发送 8. 第6步和第7步可以重复多次，即顺序写多个寄存器 9. 发起 写一个寄存器 I Read/ 四改 Data byte No ack STOP
IIC总线协议,AT24C08储存器
IIC总线协议，AT24C08储存器 -----阿拉丁神丢 IIC总线（I nter Integrated Circuit Bus）：是Philips公司推出的串行总线标准（为二线制）。总线上扩展的外围器件及外设接口通过总线寻址，是具备总线仲裁和高低速设备同步等功能的高性能多主机总线。 I2C总线工作原理 串行数据线SDA和串行时钟线SCL构成的，可发送和接收数据。 ?所有挂接在I2C总线上的器件和接口电路都应具有I2C总线接口，且所有的SDA/SCL同名端相连。总线上所有器件要依靠SDA发送的地址信号寻址，不需要片选线。 ?特点：组成系统结构简单，占用空间小，芯片管脚的数量少，无需片选信号，价格低。允许若干兼容器件共享总线，应用比较广泛。总线的长度可达7.6m，传送速度可达400kbps，标准速率为100kbps。支持多个组件。支持多主控器件（某时刻只能有一个主控器件）。I2C 总线上所有设备的SDA,SCL引脚必须外接上拉电阻。 典型的I2C总线系统结构,如图所示 I2C总线器件的寻址方式 由于所有器件都通过SCL和SDA连接在I2C总线上，因此，主器件在进行数据传输前需要通过寻址，选择需要通信的从器件。I2C总线上所有外围器件都需要有唯一的7位地址，由器件地址和引脚地址两部分组成。 器件地址是I2C器件固有的地址编码，器件出厂时就已经给定，不可更改。 引脚地址是由I2C总线外围器件的地址引脚（A2，A1，A0）决定，根据其在电路中接电源正极、接地或悬空的不同，形成不同的地址代码。
I2C总线概述 ?I2C总线采用两线制，由数据线SDA和时钟线SCL构成。I2C总线对数据通信时序进行了严格的定义。 I2C总线数据操作 在I2C总线上，数据是伴随着时钟脉冲，一位一位地传送的，数据位由高到低传送，每位数据占一个时钟脉冲。I2C总线上的在时钟线SCL高电平期间，数据线SDA的状态就表示要传送的数据，高电平为数据1，低电平为数据0。在数据传送时，SDA上数据的改变在时钟线为低电平时完成，而SCL为高电平时，SDA必须保持稳定，否则SDA上的变化会被当作起始或终止信号而致使数据传输停止。
I2C协议
I2C协议 1、I2C总线 I2C总线是由Philips公司开发的一种简单、双向二线制同步串行总线。它只需要两根线即可在连接于总线上的器件之间传送信息。 主器件用于启动总线传送数据，并产生时钟以开放传送的器件，此时任何被寻址的器件均被认为是从器件．在总线上主和从、发和收的关系不是恒定的，而取决于此时数据传送方向。如果主机要发送数据给从器件，则主机首先寻址从器件，然后主动发送数据至从器件，最后由主机终止数据传送；如果主机要接收从器件的数据，首先由主器件寻址从器件．然后主机接收从器件发送的数据，最后由主机终止接收过程。在这种情况下．主机负责产生定时时钟和终止数据传送。 主机发送数据从机找寻从机地址-主动发送数据-主机终止传送 主机接受从机数据主机找从机地址-主机接受数据-主句终止接受 2、工作原理编辑 SDA（串行数据线）和SCL（串行时钟线）都是双向I/O线，接口电路为开漏输出．需通过上拉电阻接电源VCC．当总线空闲时．两根线都是高电平，连接总线的外同器件都是CMOS器件，输出级也是开漏电路．在总线上消耗的电流很小，因此，总线上扩展的器件数量主要由电容负载来决定，因为每个器件的总线接口都有一定的等效电容．而线路中电容会影响总线传输速度．当电容过大时，有可能造成传输错误．所以，其负载能力为400pF，因此可以估算出总线允许长度和所接器件数量。 主器件用于启动总线传送数据，并产生时钟以开放传送的器件，此时任何被寻址的器件均被认为是从器件．在总线上主和从、发和收的关系不是恒定的，而取决于此时数据传送方向。如果主机要发送数据给从器件，则主机首先寻址从器件，然后主动发送数据至从器件，最后由主机终止数据传送；如果主机要接收从器件的数据，首先由主器件寻址从器件．然后主机接收从器件发送的数据，最后由主机终止接收过程。在这种情况下．主机负责产生定