AT89C51中英文翻译

The General Situation of AT89C51

1 The application of AT89C51

Microcontrollers are used in a multitude of commercial applications such as modems, motor-control systems, air conditioner control systems, automotive engine and among others. The high processing speed and enhanced peripheral set of these microcontrollers make them suitable for such high-speed event-based applications. However, these critical application domains also require that these microcontrollers are highly reliable. The high reliability and low market risks can be ensured by a robust testing process and a proper tools environment for the validation of these microcontrollers both at the component and at the system level. Intel Plaform Engineering department developed an object-oriented multi-threaded test environment for the validation of its AT89C51 automotive microcontrollers. The goals of thisenvironment was not only to provide a robust testing environment for the AT89C51 automotive microcontrollers, but to develop an environment which can be easily extended and reused for the validation of several other future microcontrollers. The environment was developed in conjunction with Microsoft Foundation Classes (AT89C51). The paper describes the design and mechanism of this test environment, its interactions with various hardware/software environmental components, and how to use AT89C51.

1.1 Introduction

The 8-bit AT89C51 CHMOS microcontrollers are designed to handle high-speedcalculations and fast input/output operations. MCS 51 microcontrollers are typically used for high-speed event control systems. Commercial applications include modems,motor-control systems, printers, photocopiers, air conditioner control systems, disk drives,and medical instruments. The automotive industry use MCS 51 microcontrollers in engine-control systems, airbags, suspension systems, and antilock braking systems (ABS). The AT89C51 is especially well suited to applications that benefit from its processing speed and enhanced on-chip peripheral functions set, such as automotive power-train control, vehicle dynamic suspension, antilock braking, and stability control applications. Because of these critical applications, the market requires a reliable cost-effective controller with a low interrupt latency response, ability to service the high number of time and event driven integrated peripherals needed in real time applications, and a CPU with above average processing power in a single package. The financial and legal risk of having devices that operate unpredictably is very high. Once in

the market, particularly in mission criticalapplications such as an autopilot or anti-lock braking system, mistakes are financiallyprohibitive. Redesign costs can run as high as a $500K, much more if the fix means 2 back annotating it across a product family that share the same core and/or peripheral design flaw. In addition, field replacements of components is extremely expensive, as the devices are typically sealed in modules with a total value several times that of the component. To mitigate these problems, it is essential that comprehensive testing of the controllers be carried out at both the component level and system level under worst case environmental and voltage conditions.This complete and thorough validation necessitates not only a well-defined process but also a proper environment and tools to facilitate and execute the mission successfully.Intel Chandler Platform Engineering group provides post silicon system validation (SV) of various micro-controllers and processors. The system validation process can be broken into three major parts.The type of the device and its application requirements determine which types of testing are performed on the device.

1.2 The AT89C51 provides the following standard features:

4Kbytes of Flash, 128 bytes of RAM, 32 I/O lines, two 16-bittimer/counters, a five vector two-level interrupt architecture,a full duple ser -ial port, on-chip oscillator and clock circuitry.In addition, the AT89C51 is designed with static logic for operation down to zero frequency and supports two software selectable power saving modes. The Idle Mode stops the CPU while allowing the RAM, timer/counters,serial port and interrupt sys -tem to continue functioning. The Power-down Mode saves the RAM contents but freezes the oscil –lator disabling all other chip functions until the next hardware reset.

Figure 1-2-1Block Diagram

1-3Pin Description

The 8-bit AT89C51 CHMOS microcontrollers are designed to handle high-speed calculations and fast input/output operations. MCS 51 microcontrollers are typically used for high-speed event control systems. Commercial applications include modems, motor-control systems, printers, photocopiers, air conditioner control systems, disk drives, and medical instruments. The automotive industry use MCS 51 microcontrollers in engine-control systems, airbags, suspension systems, and antilock braking systems (ABS). The AT89C51 is especially well suited to applications that benefit from its processing speed and enhanced on-chip peripheral functions set, such as automotive power-train control, vehicle dynamic suspension, antilock braking, and stability control applications. Because of these critical

applications, the market requires a reliable cost-effective controller with a low interrupt latency response, ability to service the high number of time and event driven integrated peripherals needed in real time applications, and a CPU with above average processing power in a single package. The financial and legal risk of having devices that operate unpredictably is very high. Once in the market, particularly in mission critical applications such as an autopilot or anti-lock braking system, mistakes are financially prohibitive. Redesign costs can run as high as a $500K, much more if the fix means back annotating it across a product family that share the same core and/or peripheral design flaw. In addition, field replacements of components is extremely expensive, as the devices are typically sealed in modules with a total value several times that of the component. To

mitigate these problems, it is essential that comprehensive testing of the controllers be carried out at both the component level and system level under worst case environmental and voltage conditions.This complete and thorough validation necessitates not only a well-defined process but also a proper environment and tools to facilitate and execute the mission successfully.

Intel Chandler Platform Engineering group provides post

silicon system validation (SV) of various micro-controllers and processors. The system validation process can be broken into three major parts.The type of the device and its application requirements determine which types of testing are performed on the device.

The AT89C51 provides the following standard features: 4Kbytes of Flash, 128 bytes of RAM, 32 I/O lines, two 16-bittimer/counters, a five vector two-level interrupt architecture,a full duple ser -ial port, on-chip oscillator and clock circuitry.In addition, the AT89C51 is designed with static logic for operation down to zero frequency and supports two software selectable power saving modes. The Idle Mode stops the CPU while allowing the RAM, timer/counters,serial port and interrupt sys -tem to continue functioning. The Power-down Mode saves the RAM contents but freezes the oscil -lator disabling all other chip functions until the next hardware reset.

VCC Supply voltage.

GND Ground.

Port 0：Port 0 is an 8-bit open-drain bi-directional I/O port. As an output port, each pin cansink eight TTL inputs. When 1s are written to port 0 pins, the pins can be used as highimpedance inputs.Port 0 may also be configured to be the multiplexed loworder address/data busduring accesses to external program and data memory. In this mode P0 has internalpullups.Port 0 also receives the code bytes during Flash programming,and outputs the codebytes during program verification. External pullups are required during programverification.

Port 1：Port 1 is an 8-bit bi-directional I/O port with internal pullups.The Port 1 output buffers can sink/so -urce four TTL inputs.When 1s are written to Port 1 pins they are pulled high by the internal pullups and can be used as inputs. As inputs, Port 1 pins that are externally being pulled low will source current (IIL) because of the internal pullups.Port 1 also receives the low-order address bytes during Flash programming and verification.

Port 2：Port 2 is an 8-bit bi-directional I/O port with internal pullups.The Port 2 outputbuffers can sink/source four TTL inputs.When 1s are written to Port 2 pins they arepulled high by the internal pullups and can be used as inputs. As inputs, Port 2 pins that are externally being pulled low will source current (IIL) because of the internal pullups. Port 2 emits the high-order address byte during fetches from external program memory and during accesses to Port 2 pins that are externally being pulled low will source current (IIL) because of the internal pullups.Port 2 emits the high-order address byte during fetches from external program memory and during accesses to external data memory that use 16-bit

addresses (MOVX@DPTR). In this application, it uses strong internal pull-ups when emitting 1s. During accesses to external data memory that use 8-bit addresses (MOVX @ RI), Port 2 emits the contents of the P2 Special Function Register.Port 2 also receives the high-order address bits and some control signals durin Flash programming and verification.

Port 3：Port 3 is an 8-bit bi-directional I/O port with internal pullups.The Port 3 outputbuffers can sink/sou -rce four TTL inputs.When 1s are written to Port 3 pins they are pulled high by the internal pullups and can be used as inputs. As inputs,Port 3 pins that are externally being pulled low will source current (IIL) because of the pullups.

Port 3 also serves the functions of various special featuresof the AT89C51 as listed below:

RST：Reset input. A high on this pin for two machine cycles while the oscillator is running resets the device.

ALE/PROG：Address Latch Enable output pulse for latching the low byte of the address duringaccesses to external memory.This pin is also the program pulse input (PROG) during Flash programming.In normal operation ALE is emitted at a constant rate of 1/6 the oscillator frequency,and may be used for external timing or clocking purposes. Note, however, that one ALEpulse is skipped duri -ng each access to external DataMemory.If desired, ALE operationcan be disabled by setting bit 0 of SFR location 8EH. With the bit set, ALE is active onlyduring a MOVX or MOVC instruction. Otherwise, the pin is weakly pulled high. Settingthe ALE-disable bit has no effect if the microcontroller is in external execution mode.

PSEN：Program Store Enable is the read strobe to external program memory. When theAT89C51 is executing code from external program memory, PSEN is activated twiceeach machine cycle, except that two PSEN activations are skipped during each access toexternal data memory.

EA/VPP：External Access Enable. EA must be strapped to GND in order to enable the deviceto fetch code from external program memory locations starting at 0000H up to FFFFH.Note, however, that if lock bit 1 is programmed, EA will be internally latched onreset.EA should be strapped to VCC for internal program executions. This pin alsreceives the 12-volt programming enable voltage (VPP) during Flash programming, forparts that require 12-volt VPP.

XTAL1：Input to the inverting oscillator amplifier and input to the internal clock operatingcircuit.

XTAL2 ：Output from the inverting oscillator amplifier.Oscillator CharacteristicsXTAL1 and XTAL2 are the input and output, respectively, of an inverting amplifierwhich can be configured for use as an on-chip oscillator, as shown in Figure 1.

Either aquartz crystal or ceramic resonator may be used. To drive the device from an externalclock source, XTAL2 should be left unconnected while XTAL1 is driven as shown in Figure 2.There are no requirements on the duty cycle of the external clock signal, since the input to the internal clocking circuitry is through a divide-by-two flip-flop, but minimum and maximum voltage high and low time specifications must be observed. Idle Mode In idle mode, the CPU puts itself to sleep while all the onchip peripherals remain active. The mode is invoked by software. The content of the on-chip RAM and all the special functions registers remain unchanged during this mode. The idle mode can be terminated by any enabled interrupt or by a hardware reset. It should be noted that when idle is terminated by a hard ware reset, the device normally resumes program execution, from where it left off, up to two machine cycles before the internal reset algorithm takes control. On-chip hardware inhibits access to internal RAM in this event, but access to the port pins is not inhibited. To eliminate the possibility of an unexpected write to a port pin when Idle is terminated by reset, the instruction following the one that invokes Idle should not be one that writes to a port pin or to external memory.

Power-down Mode

In the power-down mode, the oscillator is stopped, and the instruction that invokes power-down is the last instruction executed. The on-chip RAM and Special Function Registers retain their values until the power-down mode is terminated. The only exit from power-down is a hardware reset. Reset redefines the SFRs but does not change the on-chip RAM. The reset should not be activated before VCC is restored to its normal operating level and must be held active long enough to allow the oscillator to restart and stabilize.The AT89C51 code memory array is programmed byte-bybyte in either programming mode. To program any nonblank byte in the on-chip Flash Memory, the entire memory must be erased using the Chip Erase Mode.

2 Programming Algorithm

Before programming the AT89C51, the address, data and control signals should be set up according to the Flash programming mode table and Figure 3 and Figure 4. To program the AT89C51, take the following steps.1. Input the desired memory location on the address lines.2. Input the appropriate data byte on the data lines. 3. Activate the correct combination of control signals. 4. Raise EA/VPP to 12V for the high-voltage programming mode. 5. Pulse ALE/PROG once to program a byte in the Flash array or the lock bits. The byte-write cycle is self-timed and typically takes no more than 1.5 ms. Repeat steps 1 through 5, changing the address and data for the entire array or until the end of the object file is reached. Data Polling: The AT89C51 features Data Polling to indicate the end of a

write cycle. During a write cycle, an attempted read of the last byte written will result in the complement of the written datum on PO.7. Once the write cycle has been completed, true data are valid on all outputs, and the next cycle may begin. Data Polling may begin any time after a write cycle has been initiated.

2.1 Ready/Busy:

The progress of byte programming can also be monitored by the RDY/BSY output signal. P3.4 is pulled low after ALE goes high during programming to indicate BUSY. P3.4 is pulled high again when programming is done to indicate READY.

Program Verify:

If lock bits LB1 and LB2 have not been programmed, the programmed code data can be read back via the address and data lines for verification. The lock bits cannot be verified directly. Verification of the lock bits is achieved by observing that their features are enabled.

Figure 2-1-1 Programming the Flash Figure 2-2-2 Verifying the Flash

2.2 Chip Erase:

The entire Flash array is erased electrically by using the proper combination of control signals and by holding ALE/PROG low for 10 ms. The code array is written with all ―1‖s. The chip erase operation must be executed before the code memory can be re-programmed.

2.3 Reading the Signature Bytes:

The signature bytes are read by the same procedure as a normal verification of locations 030H, 031H, and 032H, except that P3.6 and P3.7 must be pulled to a logic low.

The values returned areas follows.

(030H) = 1EH indicates manufactured by Atmel

(031H) = 51H indicates 89C51

(032H) = FFH indicates 12V programming

(032H) = 05H indicates 5V programming

2.4 Programming Interface

Every code byte in the Flash array can be written and the entire array can be erased by using the appropriate combination of control signals. The write operation cycle is selftimed and once initiated, will automatically time itself to completion. A microcomputer interface converts information between two forms. Outside the microcomputer the information handled by an electronic system exists as a physical signal, but within the program, it is represented numerically. The function of any interface can be broken down into a number of operations which modify the data in some way, so that the process of conversion between the external and internal forms is carried out in a number of steps. An analog-to-digital converter(ADC) is used to convert a continuously variable signal to a corresponding digital form which can take any one of a fixed number of possible binary values. If the output of the transducer does not vary continuously, no ADC is necessary. In this case the signal conditioning section must convert the incoming signal to a form which can be connected directly to the next part of the interface, the input/output section of the microcomputer itself. Output interfaces take a similar form, the obvious difference being that here the flow of information is in the opposite direction; it is passed from the program to the outside world. In this case the program may call an output subroutine which supervises the operation of the interface and performs the scaling numbers which may be needed for digital-to-analog converter(DAC). This subroutine passes information in turn to an output device which produces a corresponding electrical signal, which could be converted into analog form using a DAC. Finally the signal is conditioned(usually amplified) to a form suitable for operating an actuator. The signals used within microcomputer circuits are almost always too small to be connected directly to the outside world‖ and some kind of interface must be used to translate them to a more appropriate form. The design of section of interface circuits is one of the most important tasks facing the engineer wishing to apply microcomputers. We have seen that in microcomputers information is represented as discrete patterns of bits; this digital form is most useful when the microcomputer is to be connected to equipment which can only be switched on or off, where each bit might represent the state of a switch or actuator. To solve real-world

problems, a microcontroller must have more than just a CPU, a program, and a data memory. In addition, it must contain hardware allowing the CPU to access information from the outside world. Once the CPU gathers information and processes the data, it must also be able to effect change on some portion of the outside world. These hardware devices, called peripherals, are the CPU’s window to the outside.

The most basic form of peripheral available on microcontrollers is the general purpose I70 port. Each of the I/O pins can be used as either an input or an output. The function of each pin is determined by setting or clearing corresponding bits in a corresponding data direction register during the initialization stage of a program. Each output pin may be driven to either a logic one or a logic zero by using CPU instructions to pin may be viewed (or read.) by the CPU using program instructions. Some type of serial unit is included on microcontrollers to allow the CPU to communicate bit-serially with external devices. Using a bit serial format instead of bit-parallel format requires fewer I/O pins to perform the communication function, which makes it less expensive, but slower. Serial transmissions are performed either synchronously or asynchronously.

AT89C51的概况

1 AT89C51应用

单片机广泛应用于商业：诸如调制解调器，电动机控制系统，空调控制系统，汽车发动机和其他一些领域。这些单片机的高速处理速度和增强型外围设备集合使得它们适合于这种高速事件应用场合。然而，这些关键应用领域也要求这些单片机高度可靠。健壮的测试环境和用于验证这些无论在元部件层次还是系统级别的单片机的合适的工具环境保证了高可靠性和低市场风险。Intel 平台工程部门开发了一种面向对象的用于验证它的AT89C51 汽车单片机多线性测试环境。这种环境的目标不仅是为AT89C51 汽车单片机提供一种健壮测试环境，而且开发一种能够容易扩展并重复用来验证其他几种将来的单片机。开发的这种环境连接了AT89C51。本文讨论了这种测试环境的设计和原理，它的和各种硬件、软件环境部件的交互性，以及如何使用AT89C51。

1.1 介绍

8 位AT89C51 CHMOS 工艺单片机被设计用于处理高速计算和快速输入/输出。MCS51 单片机典型的应用是高速事件控制系统。商业应用包括调制解调器，电动机控制系统，打印机，影印机，空调控制系统，磁盘驱动器和医疗设备。汽车工业把MCS51 单片机用于发动机控制系统，悬挂系统和反锁制动系统。AT89C51 尤其很好适用于得益于它的处理速度和增强型片上外围功能集，诸如：汽车动力控制，车辆动态悬挂，反锁制动和稳定性控制应用。由于这些决定性应用，市场需要一种可靠的具有低干扰潜伏响应的费用-效能控制器，服务大量时间和事件驱动的在实时应用需要的集成外围的能力，具有在单一程序包中高出平均处理功率的中央处理器。拥有操作不可预测的设备的经济和法律风险是很高的。一旦进入市场，尤其任务决定性应用诸如自动驾驶仪或反锁制动系统，错误将是财力上所禁止的。重新设计的费用可以高达500K 美元，如果产品族享有同样内核或外围设计缺陷的话，费用会更高。另外，部件的替代品领域是极其昂贵的，因为设备要用来把模块典型地焊接成一个总体的价值比各个部件高几倍。为了缓和这些问题，在最坏的环境和电压条件下对这些单片机进

行无论在部件级别还是系统级别上的综合测试是必需的。Intel Chandler 平台工程组提供了各种单片机和处理器的系统验证。这种系统的验证处理可以被分解为三个主要部分。系统的类型和应用需求决定了能够在设备上执行的测试类型。

1.2 AT89C51提供以下标准功能：

4k 字节FLASH 闪速存储器，128 字节内部RAM，32 个I/O 口线，2 个16 位定时/计数器，一个5 向量两级中断结构，一个全双工串行通信口，片内振荡器及时钟电路。同时，AT89C51 降至0Hz 的静态逻辑操作，并支持两种可选的节电工作模式。空闲方式体制CPU 的工作，但允许RAM，定时/计数器，串行通信口及中断系统继续工作。掉电方式保存RAM 中的内容，但振荡器体制工作并禁止其他所有不见工作直到下一个硬件复位。

图1-2-1 AT89C51 方框图

1.3 引脚功能说明

8位AT89C51 CHMOS工艺单片机被设计用于处理高速计算和快速输入/输出。MCS51单片机典型的应用是高速事件控制系统。商业应用包括调制解调器，电动机控

制系统，打印机，影印机，空调控制系统，磁盘驱动器和医疗设备。汽车工业把MCS51单片机用于发动机控制系统，悬挂系统和反锁制动系统。AT89C51尤其很好适用于得益于它的处理速度和增强型片上外围功能集，诸如：汽车动力控制，车辆动态悬挂，反锁制动和稳定性控制应用。由于这些决定性应用，市场需要一种可靠的具有低干扰潜伏响应的费用-效能控制器，服务大量时间和事件驱动的在实时应用需要的集成外围的能力，具有在单一程序包中高出平均处理功率的中央处理器。拥有操作不可预测的设备的经济和法律风险是很高的。一旦进入市场，尤其任务决定性应用诸如自动驾驶仪或反锁制动系统，错误将是财力上所禁止的。重新设计的费用可以高达500K美元，如果产品族享有同样内核或外围设计缺陷的话，费用会更高。另外，部件的替代品领域是极其昂贵的，因为设备要用来把模块典型地焊接成一个总体的价值比各个部件高几倍。为了缓和这些问题，在最坏的环境和电压条件下对这些单片机进行无论在部件级别还是系统级别上的综合测试是必需的。Intel Chandler平台工程组提供了各种单片机和处理器的系统验证。这种系统的验证处理可以被分解为三个主要部分。系统的类型和应用需求决定了能够在设备上执行的测试类型。

AT89C51提供以下标准功能：4k 字节FLASH闪速存储器，128字节内部RAM，32个I/O口线，2个16位定时/计数器，一个5向量两级中断结构，一个全双工串行通信口，片内振荡器及时钟电路。同时，AT89C51降至0Hz的静态逻辑操作，并支持两种可选的节电工作模式。空闲方式体制CPU的工作，但允许RAM，定时/计数器，串行通信口及中断系统继续工作。掉电方式保存RAM中的内容，但振荡器体制工作并禁止其他所有不见工作直到下一个硬件复位。

·Vcc：电源电压

·GND：地

·P0 口：P0 口是一组8 位漏极开路型双向I/O 口，也即地址/数据总线复用。作为输出口用时，每位能吸收电流的方式驱动8 个TTL 逻辑门电路，对端口写―1‖可作为高阻抗输入端用。在访问外部数据存储器或程序存储器时，这组口线分时转换地址（低8 位）和数据总线复用，在访问期间激活内部上拉电阻。在Flash 编程时，P0 口接受指令字节，而在程序校验时，输出指令字节，校验时，要求外接上拉电阻。

·P1 口：P1 是一个带内部上拉电阻的8 位双向I/O 口，P1 的输出缓冲级可驱动（吸收或输出电流）4 个TTL 逻辑门电路。对端口写―1‖，通过内部的上拉电阻把端口拉到高电平，此时可作输入口。作为输入口使用时，因为内部存在上拉电阻，某个引脚被外部信号拉低时会输出一个电流（IIL）。Flash 编程和程序校验期间，P1 接受低8 位地址。

·P2 口：P2 是一个带有内部上拉电阻的8 位双向I/O 口，P2 的输出缓冲级可驱动（吸收或输出电流）4 个TTL 逻辑门电路。对端口写―1‖，通过内部的上拉电阻把端口拉到高电平，此时可作输入口。作为输入口使用时，因为内部存在上拉电阻，某个引脚被外部信号拉低时会输出一个电流（IIL）。在访问外部程序存储器或16 位四

肢的外部数据存储器（例如执行MOVX @DPTR指令）时，P2 口送出高8 位地址数据，在访问8 位地址的外部数据存储器（例如执行MOVX @ RI 指令）时，P2 口线上的内容（也即特殊功能寄存器（SFR）区中R2 寄存器的内容），在整个访问期间不改变。Flash 编程和程序校验时，P2 也接收高位地址和其他控制信号。

·P3 口：P3 是一个带有内部上拉电阻的8 位双向I/O 口，P3 的输出缓冲级可驱动（吸收或输出电流）4 个TTL 逻辑门电路。对端口写―1‖，通过内部的上拉电阻把端口拉到高电平，此时可作输入口。作为输入口使用时，因为内部存在上拉电阻，某个引脚被外部信号拉低时会输出一个电流（IIL）。P3 口还接收一些用于Flash 闪速存储器编程和程序校验的控制信号。

·RST：复位输入。当振荡器工作时，RST 引脚出现两个机器周期以上高电平将使单片机复位。

·ALE/PROG：当访问外部程序存储器或数据存储器时，ALE（地址锁存允许）输出脉冲用于锁存地址的低8 位字节。即使不访问外部存储器，ALE 仍以时钟振荡频率的1/6 输出固定的正脉冲信号，因此它可对外输出时钟或用于定时目的。要注意的是，每当访问外部数据存储器时将跳过一个ALE 脉冲。对Flash 存储器编程期间，该引脚还用于输入编程脉冲（PROG）。如有必要，可通过对特殊功能寄存器（SFR）区中的8EH 单元D0 位置位，可禁止ALE 操作。该位置位后，只有一条MOVX 和MOVC 指令ALE 才会被激活。此外，该引脚会被微弱拉高，单片机执行外部程序时，应设置ALE 无效。

·PSEN：程序存储允许输出是外部程序存储器的读选通型号，当89C51 由外部存储器取指令（或数据）时，每个机器周期两次PSEN 有效，即输出两个脉冲。在此期间，当访问外部数据存储器，这两次有效的PSEN 信号不出现。

·EA/VPP：外部访问允许。欲使CPU 仅访问外部程序存储器（地址为

0000H—FFFFH），EA 端必须保持低电平（接地）。需注意的是：如果加密位LB1 被编程，复位时内部会锁存EA 端状态。如EA 端为高电平（接Vcc 端），CPU 则执行内部程序存储器中的指令。Flash 存储器编程时，该引脚加上+12v 的编程允许电源Vpp，当然这必须是该器件使用12v 编程电压Vpp。

·XTAL1：振荡器反相放大器及内部时钟发生器的输入端。

·XTAL2：振荡器反相放大器的输出端。89C51 中有一个用于构成内部振荡器的高增益反相放大器，引脚XTAL1 和XTAL2分别是该放大器的输入端和输出端。这个

放大器与作为反馈元件的片外石英晶体或陶瓷谐振器一起构成自激振荡器，振荡电路参见图5。外接石英晶体或陶瓷谐振器及电容C1、C2 接在放大器的反馈回路中构成并联振荡电路。对电容C1、C2 虽没有十分严格的要求，但电容容量的大小会轻微影响振荡频率的高低、振荡器工作的稳定性、起振的难易程度及温度稳定性，如果使用石英晶体，我们推荐电容使用30Pf±10 Pf，而如使用陶瓷谐振器建议选择40Pf±10Pf。用户也可以采用外部时钟。这种情况下，外部时钟脉冲接到XTAL1 端，即内部时钟发生器的输入端XTAL2 则悬空。

·掉电模式：

在掉电模式下，振荡器停止工作，进入掉电模式的指令是最后一条被执行的指令，片内RAM 和特殊功能寄存器的内容在终止掉电模式前被冻结。推出掉电模式的唯一方法是硬件复位，复位后将重新定义全部特殊功能寄存器但不改变RAM 中的内容，在Vcc 恢复到正常工作电平前，复位应无效，且必须保持一定时间以使振荡器重启动并稳定工作。89C51 的程序存储器阵列是采用字节写入方式编程的，每次写入一个字符，要对整个芯片的EPROM 程序存储器写入一个非空字节，必须使用片擦除的方法将整个存储器的内容清楚。

2 编程方法

编程前，设置好地址、数据及控制信号，编程单元的地址加在P1 口和P2 口的P2.0—P2.3（11 位地址范围为0000H——0FFFH），数据从P0口输入，引脚P2.6、P2.7 和P3.6、P3.7 的电平设置见表6，PSEB 为低电平，RST保持高电平，EA/Vpp 引脚是编程电源的输入端，按要求加上编程电压，ALE/PROG引脚输入编程脉冲（负脉冲）。编程时，可采用4—20MHz 的时钟振荡器，89C51 编程方法如下：在地址线上加上要编程单元的地址信号在数据线上加上要写入的数据字节。激活相应的控制信号。在高电压编程方式时，将EA/Vpp 端加上+12v 编程电压。每对Flash 存储阵列写入一个字节或每写入一个程序加密位，加上一个ALE/PROG 编程脉冲。改变编程单元的地址和写入的数据，重复1—5 步骤，知道全部文件编程结束。每个字节写入周期是自身定时的，通常约为1.5ms。·数据查询89C51 单片机用数据查询方式来检测一个写周期是否结束，在一个写周期中，如需要读取最后写入的那个字节，则读出的数据的最

高位（P0.7）是原来写入字节的最高位的反码。写周期开始后，可在任意时刻进行数据查询。

2.1 Ready/Busy

字节编程的进度可通过Ready/Busy 输出信号检测，编程期间，ALE 变为高电平―H‖后P3.4（Ready/Busy）端被拉低，表示正在编程状态（忙状态）。编程完成后，P3.4 变为高电平表示准备就绪状态。

·程序校验：如果加密位LB、LB2 没有进行编程，则代码数据可通过地址和数据线读回原编写的数据，采用下图的电路，程序存储器的地址由P1 口和P2 口的P2.0—P2.3 输入，数据由P0 口读出，P206、P2.7 和P3.6、P3.7 的控制信号见表6，PSEN 保持低电平，ALE、EA 和RST 保持高电平。校验时，P0 口必须接上10k 左右的上拉电阻。

图2-1-1 编程电路图2-2-2 校验电路

2.2 芯片擦除

利用控制信号的正确组合(表6)并保持ALE/PROG 引脚10ms 的低电平脉冲宽度即可将EPROM 阵列(4k 字节)和三个加密位整片擦除,代码阵列在片擦除操作中将任何非空单元写入‖1‖,这步骤需在编程之前进行。

2.3 读片内签名字节:

89C51 单片机内有3 个签名字节,地址为030H、031H 和032H。于声明该器件的

厂商、号和编程电压。读签名字节的过程和单元030H、031H 和032H的正常校验相仿，只需要将P3.6 和P3.7 保持低电平，返回值意义如下：

(030H) = 1EH 声明产品由ATMEL 公司制造。

(031H) = 51H 声明为89C51 单片机。

(032H) = FFH 声明为12V 编程电压。

(032H) = 05H 声明为5 编程电压。

2.4 编程接口：

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单片机可利用外围设备中最基本的用于一般用途的I/O 接口，每个I/O 接口既可

作为输入端又可作为输出端，每个I/O 接口的功能取决与程序初始化阶段对数据方位寄存器相应位进行置一和清零操作，通过CPU 指令对数据寄存器相应位进行置一和清零来置一和清零输出端口，同样输入端口逻辑位也可以通过CPU 指令访问。一些类型的串行口单元允许CPU 与外部设备进行串口通信，用串口位代替平行位进行通信需要少许的I/O 口，这样使通信费用降低但速度也相对慢些。串口传送可以同步也可以异步。

机械手机械设计论文中英文资料对照外文翻译

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中等分辨率制备分离的 快速色谱技术 W. Clark Still,* Michael K a h n , and Abhijit Mitra Departm(7nt o/ Chemistry, Columbia Uniuersity,1Veu York, Neu; York 10027 ReceiLied January 26, 1978 我们希望找到一种简单的吸附色谱技术用于有机化合物的常规净化。这种技术是适于传统的有机物大规模制备分离，该技术需使用长柱色谱法。尽管这种技术得到的效果非常好，但是其需要消耗大量的时间，并且由于频带拖尾经常出现低复原率。当分离的样本剂量大于1或者2g时，这些问题显得更加突出。近年来，几种制备系统已经进行了改进，能将分离时间减少到1-3h，并允许各成分的分辨率ΔR f≥（使用薄层色谱分析进行分析）。在这些方法中，在我们的实验室中，媒介压力色谱法1和短柱色谱法2是最成功的。最近，我们发现一种可以将分离速度大幅度提升的技术，可用于反应产物的常规提纯，我们将这种技术称为急骤色谱法。虽然这种技术的分辨率只是中等（ΔR f≥），而且构建这个系统花费非常低，并且能在10-15min内分离重量在的样本。4 急骤色谱法是以空气压力驱动的混合介质压力以及短柱色谱法为基础，专门针对快速分离，介质压力以及短柱色谱已经进行了优化。优化实验是在一组标准条件5下进行的，优化实验使用苯甲醇作为样本，放在一个20mm*5in.的硅胶柱60内，使用Tracor 970紫外检测器监测圆柱的输出。分辨率通过持续时间（r）和峰宽（w,w/2）的比率进行测定的（Figure 1），结果如图2-4所示，图2-4分别放映分辨率随着硅胶颗粒大小、洗脱液流速和样本大小的变化。

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机械设计外文翻译(中英文)

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土木工程外文文献翻译

专业资料 学院： 专业：土木工程 姓名： 学号： 外文出处：Structural Systems to resist (用外文写) Lateral loads 附件：1.外文资料翻译译文；2.外文原文。

附件1：外文资料翻译译文 抗侧向荷载的结构体系 常用的结构体系 若已测出荷载量达数千万磅重，那么在高层建筑设计中就没有多少可以进行极其复杂的构思余地了。确实，较好的高层建筑普遍具有构思简单、表现明晰的特点。 这并不是说没有进行宏观构思的余地。实际上，正是因为有了这种宏观的构思，新奇的高层建筑体系才得以发展，可能更重要的是：几年以前才出现的一些新概念在今天的技术中已经变得平常了。 如果忽略一些与建筑材料密切相关的概念不谈，高层建筑里最为常用的结构体系便可分为如下几类： 1.抗弯矩框架。 2.支撑框架，包括偏心支撑框架。 3.剪力墙，包括钢板剪力墙。 4.筒中框架。 5.筒中筒结构。 6.核心交互结构。 7. 框格体系或束筒体系。 特别是由于最近趋向于更复杂的建筑形式，同时也需要增加刚度以抵抗几力和地震力，大多数高层建筑都具有由框架、支撑构架、剪力墙和相关体系相结合而构成的体系。而且，就较高的建筑物而言，大多数都是由交互式构件组成三维陈列。 将这些构件结合起来的方法正是高层建筑设计方法的本质。其结合方式需要在考虑环境、功能和费用后再发展，以便提供促使建筑发展达到新高度的有效结构。这并

不是说富于想象力的结构设计就能够创造出伟大建筑。正相反，有许多例优美的建筑仅得到结构工程师适当的支持就被创造出来了，然而，如果没有天赋甚厚的建筑师的创造力的指导，那么，得以发展的就只能是好的结构，并非是伟大的建筑。无论如何，要想创造出高层建筑真正非凡的设计，两者都需要最好的。 虽然在文献中通常可以见到有关这七种体系的全面性讨论，但是在这里还值得进一步讨论。设计方法的本质贯穿于整个讨论。设计方法的本质贯穿于整个讨论中。 抗弯矩框架 抗弯矩框架也许是低，中高度的建筑中常用的体系，它具有线性水平构件和垂直构件在接头处基本刚接之特点。这种框架用作独立的体系，或者和其他体系结合起来使用，以便提供所需要水平荷载抵抗力。对于较高的高层建筑，可能会发现该本系不宜作为独立体系，这是因为在侧向力的作用下难以调动足够的刚度。 我们可以利用STRESS，STRUDL 或者其他大量合适的计算机程序进行结构分析。所谓的门架法分析或悬臂法分析在当今的技术中无一席之地，由于柱梁节点固有柔性，并且由于初步设计应该力求突出体系的弱点，所以在初析中使用框架的中心距尺寸设计是司空惯的。当然，在设计的后期阶段，实际地评价结点的变形很有必要。 支撑框架 支撑框架实际上刚度比抗弯矩框架强，在高层建筑中也得到更广泛的应用。这种体系以其结点处铰接或则接的线性水平构件、垂直构件和斜撑构件而具特色，它通常与其他体系共同用于较高的建筑，并且作为一种独立的体系用在低、中高度的建筑中。

网络安全外文翻译文献

网络安全外文翻译文献 (文档含英文原文和中文翻译) 翻译： 计算机网络安全与防范 1.1引言 计算机技术的飞速发展提供了一定的技术保障，这意味着计算机应用已经渗透到社会的各个领域。在同一时间，巨大的进步和网络技术的普及，社会带来了巨大的经济利润。然而，在破坏和攻击计算机信息系统的方法已经改变了很多的网络环境下，网络安全问题逐渐成为计算机安全的主流。

1.2网络安全 1.2.1计算机网络安全的概念和特点 计算机网络的安全性被认为是一个综合性的课题，由不同的人，包括计算机科学、网络技术、通讯技术、信息安全技术、应用数学、信息理论组成。作为一个系统性的概念，网络的安全性由物理安全、软件安全、信息安全和流通安全组成。从本质上讲，网络安全是指互联网信息安全。一般来说，安全性、集成性、可用性、可控性是关系到网络信息的相关理论和技术，属于计算机网络安全的研究领域。相反，狭隘“网络信息安全”是指网络安全，这是指保护信息秘密和集成，使用窃听、伪装、欺骗和篡夺系统的安全性漏洞等手段，避免非法活动的相关信息的安全性。总之，我们可以保护用户利益和验证用户的隐私。 计算机网络安全有保密性、完整性、真实性、可靠性、可用性、非抵赖性和可控性的特点。 隐私是指网络信息不会被泄露给非授权用户、实体或程序，但是授权的用户除外，例如，电子邮件仅仅是由收件人打开，其他任何人都不允许私自这样做。隐私通过网络信息传输时，需要得到安全保证。积极的解决方案可能会加密管理信息。虽然可以拦截，但它只是没有任何重要意义的乱码。 完整性是指网络信息可以保持不被修改、破坏，并在存储和传输过程中丢失。诚信保证网络的真实性，这意味着如果信息是由第三方或未经授权的人检查，内容仍然是真实的和没有被改变的。因此保持完整性是信息安全的基本要求。 可靠性信息的真实性主要是确认信息所有者和发件人的身份。 可靠性表明该系统能够在规定的时间和条件下完成相关的功能。这是所有的网络信息系统的建立和运作的基本目标。 可用性表明网络信息可被授权实体访问，并根据自己的需求使用。 不可抵赖性要求所有参加者不能否认或推翻成品的操作和在信息传输过程中的承诺。

机械专业外文翻译中英文翻译

外文翻译 英文原文 Belt Conveying Systems Development of driving system Among the methods of material conveying employed，belt conveyors play a very important part in the reliable carrying of material over long distances at competitive cost．Conveyor systems have become larger and more complex and drive systems have also been going through a process of evolution and will continue to do so．Nowadays，bigger belts require more power and have brought the need for larger individual drives as well as multiple drives such as 3 drives of 750 kW for one belt(this is the case for the conveyor drives in Chengzhuang Mine)．The ability to control drive acceleration torque is critical to belt conveyors’ performance．An efficient drive system should be able to provide smooth，soft starts while maintaining belt tensions within the specified safe limits．For load sharing on multiple drives．torque and speed control are also important consideratio ns in the drive system’s design. Due to the advances in conveyor drive control technology，at present many more reliable．Cost-effective and performance-driven conveyor drive systems cov ering a wide range of power are available for customers’ choices[1]. 1 Analysis on conveyor drive technologies 1．1 Direct drives Full-voltage starters．With a full-voltage starter design，the conveyor head shaft is direct-coupled to the motor through the gear drive．Direct full-voltage starters are adequate for relatively low-power, simple-profile conveyors．With direct fu11-voltage starters．no control is provided for various conveyor loads and．depending on the ratio between fu11- and no-1oad power requirements，empty starting times can be three or four times faster than full load．The maintenance-free starting system is simple，low-cost and very reliable．However, they cannot control starting torque and maximum stall torque；therefore．they are

框架结构设计外文翻译

毕业设计(论文)外文资料翻译 系：机械工程系 专业：土木工程 姓名： 学号： 外文出处：Design of prestressed (用外文写) concrete structures 附件： 1.外文资料翻译译文；2.外文原文。

附件1：外文资料翻译译文 8-2简支梁布局 一个简单的预应力混凝土梁由两个危险截面控制：最大弯矩截面和端截面。这两部分设计好之后，中间截面一定要单独检查，必要时其他部位也要单独调查。最大弯矩截面在以下两种荷载阶段为控制情况，即传递时梁受最小弯矩M G的初始阶段和最大设计弯矩M T时的工作荷载阶段。而端截面则由抗剪强度、支承垫板、锚头间距和千斤顶净空所需要的面积来决定。所有的中间截面是由一个或多个上述要求，根它们与上述两种危险截面的距离来控制。对于后张构件的一种常见的布置方式是在最大弯矩截面采用诸如I形或T形的截面，而在接近梁端处逐渐过渡到简单的矩形截面。这就是人们通常所说的后张构件的端块。对于用长线法生产的先张构件，为了便于生产，全部只用一种等截面，其截面形状则可以为I形、双T形或空心的。在第5 、 6 和7章节中已经阐明了个别截面的设计，下面论述简支梁钢索的总布置。 梁的布置可以用变化混凝土和钢筋的办法来调整。混凝土的截面在高度、宽度、形状和梁底面或者顶面的曲率方面都可以有变化。而钢筋只在面积方面有所变化，不过在相对于混凝土重心轴线的位置方面却多半可以有变化。通过调整这些变化因素，布置方案可能有许多组合，以适应不同的荷载情况。这一点是与钢筋混凝土梁是完全不同的，在钢筋混凝土梁的通常布置中，不是一个统一的矩形截面便是一个统一的T形，而钢筋的位置总是布置得尽量靠底面纤维。 首先考虑先张梁，如图 8-7，这里最好采用直线钢索，因为它们在两个台座之间加力比较容易。我们先从图（a）的等截面直梁的直线钢索开始讨论。这样的布置都很简单，但这样一来，就不是很经济的设计了，因为跨中和梁端的要求会产生冲突。通常发生在跨度中央的最大弯矩截面中的钢索，最好尽量放低，以便尽可能提供最大力臂而提供最大的内部抵制力矩。当跨度中央的梁自重弯矩M G相当大时，就可以把c.g.s布置在截面核心范围以下很远的地方，而不致在传递时在顶部纤维中引起拉应力。然而对于梁端截面却有一套完全不同的要求。由于在梁端没有外力矩，因为在最后的时刻，安排钢索要以c.g.s与 c.g.c在结束区段一致，如此同样地获得克服压力分配的方法。无论如何，如果张应力在最后不能承受，放置 c.g.s.

网络安全中的中英对照

网络安全中的中英对照 Access Control List（ACL）访问控制列表 access token 访问令牌 account lockout 帐号封锁 account policies 记帐策略 accounts 帐号 adapter 适配器 adaptive speed leveling 自适应速率等级调整 Address Resolution Protocol(ARP) 地址解析协议Administrator account 管理员帐号 ARPANET 阿帕网（internet的前身） algorithm 算法 alias 别名 allocation 分配、定位 alias 小应用程序 allocation layer 应用层 API 应用程序编程接口 anlpasswd 一种与Passwd+相似的代理密码检查器 applications 应用程序 ATM 异步传递模式

audio policy 审记策略 auditing 审记、监察 back-end 后端 borde 边界 borde gateway 边界网关 breakabie 可破密的 breach 攻破、违反 cipher 密码 ciphertext 密文 CAlass A domain A类域 CAlass B domain B类域 CAlass C domain C类域 classless addressing 无类地址分配 cleartext 明文 CSNW Netware客户服务 client 客户，客户机 client/server 客户机/服务器 code 代码 COM port COM口（通信端口） CIX 服务提供者 computer name 计算机名

外文翻译英文

A Distributed Approach for Track Occupancy Detection Abstract This paper investigates the problem of track occupancy detection in distributed settings. Track occupancy detection determines which tracks are occupied in a railway system. For each track, the Neyman–Pearson structure is applied to reach the local decision. Globally, it is a multiple hypotheses testing problem. The Bayesian approach is employed to minimize the probability of the global decision error. Based on the prior probabilities of multiple hypotheses and the approximation of the prior probabilities of multiple hypotheses and the approximationofthereceiving operation characteristic curve of the local detector, a person-by-person optimization method is implemented to obtain the fusion rule and the local strategies off line. The results are illustrated through an example constructed from in situ devices. Key Words:Track occupancy detection,Neyman–Pearson, Generalized likelihood ratio test, Bayesian approach,Distributed detection 1Introduction With respect to the majority of railway systems in China, a quasi-moving block method is employed to specify the safe zone of a train. A key piece of knowledge to be determined is the set of track segments that are occupied, i.e., track occupancy detection. Then the speed restriction curves for the following trains are calculated accordingly. When there are misdetections, collisions may happen; additionally, false alarms may lead to declines of line capacity. Track occupancy detection is achieved by a set of track circuits. The track circuit is a crucial device mainly composed of a transmitter–receiver pair and a track segment. The measurement is the receiving signal at the end of the track. For each segment, a decision is made locally and individually, which leads to frequent ambiguities on which tracks are occupied for the whole line. It means that the false alarm rate of the line increases greatly. Besides, for the next generation of railway systems, a moving block method is adopted. Such a method requires the exact position and velocity of the train. However, those data are not provided in the current detection mechanism.

网络安全外文翻译--APR欺骗检测：一种主动技术手段

外文翻译原文及译文 学院计算机学院 专业计算机科学与技术班级 学号 姓名 指导教师 负责教师 2011年6月

Detecting ARP Spoofing: An Active Technique Vivek Ramachandran and Sukumar Nandi Cisco Systems, Inc., Bangalore India Indian Institute of Technology, Guwahati, Assam, India Abstract. The Address Resolution Protocol (ARP) due to its statelessness and lack of an authentication mechanism for verifying the identity of the sender has a long history of being prone to spoofing attacks. ARP spoofing is sometimes the starting point for more sophisticated LAN attacks like denial of service, man in the middle and session hijacking. The current methods of detection use a passive approach, monitoring the ARP traffic and looking for inconsistencies in the Ethernet to IP address mapping. The main drawback of the passive approach is the time lag between learning and detecting spoofing. This sometimes leads to the attack being discovered long after it has been orchestrated. In this paper, we present an active technique to detect ARP spoofing. We inject ARP request and TCP SYN packets into the network to probe for inconsistencies. This technique is faster, intelligent, scalable and more reliable in detecting attacks than the passive methods. It can also additionally detect the real mapping of MAC to IP addresses to a fair degree of accuracy in the event of an actual attack. 1. Introduction The ARP protocol is one of the most basic but essential protocols for LAN communication. The ARP protocol is used to resolve the MAC address of a host given its IP address. This is done by sending an ARP request packet (broadcasted) on the network. The concerned host now replies back with its MAC address in an ARP reply packet (unicast). In some situations a host might broadcast its own MAC address in a special Gratuitous ARP packet. All hosts maintain an ARP cache where all address mappings

机械图纸中英文翻译汇总

近几年，我厂和英国、西班牙的几个公司有业务往来，外商传真发来的图纸都是英文标注，平时阅看有一定的困难。下面把我们积累的几点看英文图纸的经验与同行们交流。 1标题栏 英文工程图纸的右下边是标题栏（相当于我们的标题栏和部分技术要求），其中有图纸名称（TILE）、设计者（DRAWN）、审查者（CHECKED）、材料（MATERIAL）、日期（DATE）、比例（SCALE）、热处理（HEAT TREATMENT）和其它一些要求，如： 1)TOLERANCES UNLESS OTHERWISE SPECIFIAL 未注公差。 2)DIMS IN mm UNLESS STATED 如不做特殊要求以毫米为单位。 3)ANGULAR TOLERANCE±1°角度公差±1°。 4)DIMS TOLERANCE±0.1未注尺寸公差±0.1。 5)SURFACE FINISH 3.2 UNLESS STATED未注粗糙度3.2。 2常见尺寸的标注及要求 2.1孔（HOLE）如： （1）毛坯孔：3"DIAO+1CORE 芯子3"0+1; （2）加工孔：1"DIA1"; （3）锪孔：锪孔(注C＇BORE=COUNTER BORE锪底面孔); （4）铰孔：1"/4 DIA REAM铰孔1"/4; （5）螺纹孔的标注一般要表示出螺纹的直径，每英寸牙数（螺矩）、螺纹种类、精度等级、钻深、攻深，方向等。如： 例1.6 HOLES EQUI-SPACED ON 5"DIA (6孔均布在5圆周上（EQUI-SPACED=EQUALLY SPACED均布） DRILL 1"DIATHRO＇ 钻1"通孔（THRO＇=THROUGH通） C/SINK22×6DEEP 沉孔22×6 例2.TAP7"/8-14UNF-3BTHRO＇ 攻统一标准细牙螺纹，每英寸14牙，精度等级3B级 （注UNF=UNIFIED FINE THREAD美国标准细牙螺纹） 1"DRILL 1"/4-20 UNC-3 THD7"/8 DEEP 4HOLES NOT BREAK THRO钻 1"孔，攻1"/4美国粗牙螺纹，每英寸20牙，攻深7"/8,4孔不准钻通（UNC=UCIFIED COARSE THREAD 美国标准粗牙螺纹）

外文翻译(英文)

Title: Modelling of transport costs and logistics for on-farm milk segregation in New Zealand dairying Material Source: Computers and Electronics in Agriculture Author: A. E. Dooley, Parker, H. T. Blair Abstract On-farm milk segregation to keep milk with high value properties separate from bulk milk will affect transport logistics. Separate milk collection, either as independent runs for different milk types,or storage of distinct milk types in the truck and trailer units, may increase the length and number of runs required. Two contrasting regions,with different farm sizes and roading networks were modelled,at two stages of lactation over 20 years. Thirty farms in each region were modelled with 0, 25, 50 and 100% of farms per region changing milk types over a transition period of up to 18 years. Genetic algorithm software was used to search for the order of the farm milk collection pick-ups which gave an optimal, least cost solution for milk collection for each prescribed set of inputs. Milk collection costs within scenario were variable over time depending on the amounts of the different milk types, increasing whenever another run was required, then decreasing over time as the milk load increased. Milk collection cost is small relative to milk income, with the status quo (SQ) cost for milk collection being less than NZ$9.61/kl for the North Island and NZ$13.53/kl for the South Island farm sets. The increased transport costs associated with collecting two milk types ranged from 4.5 to 22.0% more for the different scenarios. The extra cost to an average size North Island farm changing systems (25% farms changing), compared to an equivalent status quo farm, would be between NZ$307 and NZ$1244 per year. Fewer farms changing to differentiated milk production increased the costs per kilolitre of differentiated milk. Keywords: Milk transport; Scheduling; Milk segregation; Collection costs 1.Introduction

浅析网络安全的技术-毕业设计(论文)外文翻译 (2)

附件1 外文资料翻译译文： 浅析网络安全的技术 过去两个世纪中，工业技术代表了一个国家的军事实力和经济实力。飞速发展的今天，对信息技术的掌握是在二十一世纪增强综合国力的关键。 随着计算机技术的发展，在计算机上处理业务已由基于单机的数学运算、文件处理，基于简单连结的内部网络的内部业务处理、办公自动化等发展到基于企业复杂的内部网、企业外部网?、全球互联网的企业级计算机处理系统和世界范围内的信息共享和业务处理。在信息处理能力提高的同时，系统的连结能力也在不断的提高。但在连结信息能力、流通能力提高的同时，基于网络连接的安全问题也日益突出。本文主要从以下几个方面进行探讨： 一、网络在开放的同时存在的安全问题 Internet的开放性以及其他方面因素导致了网络环境下的计算机系统存在很多安全问题。为了解决这些安全问题，各种安全机制、策略和工具被研究和应用。然而，即使在使用了现有的安全工具和机制的情况下，网络的安全仍然存在很大隐患，这些安全隐患主要可以归结为以下几点： 1)安全机制的局限 每一种安全机制都有一定的应用范围和应用环境。防火墙是一种有效的安全工具，它可以隐蔽内部网络结构，限制外部网络到内部网络的访问。但是对于内部网络之间的访问，防火墙往往是无能为力的。因此，对于内部网络到内部网络之间的入侵行为和内外勾结的入侵行为，防火墙是很难发觉和防范的。 2)安全管理机制的建立 常用的安全管理机制有：口令管理;各种密钥的生成、分发与管理;全网统一的管理员身份鉴别与授权;建立全系统的安全评估体系;建立安全审计制度;建立系统及数据的备份制度;建立安全事件/安全报警反应机制和处理预案;建立专门的安全问题小组和快速响应体系的运作等。 为了增强系统的防灾救灾能力,还应制定灾难性事故的应急计划,如紧急行动方案,资源(硬件,软件,数据等)备份及操作计划,系统恢复和检测方法等。 3)安全工具的影响