AT89C51的介绍外文翻译1
AT89C51的介绍
描述：
AT89C51是一个低电压，高性能CMOS8位单片机带有4K字节的可反复擦写的程序存储器（PENROM）。和128字节的存取数据存储器（RAM），这种器件采用ATMEL公司的高密度、不容易丢失存储技术生产，并且能够与MCS-51系列的单片机兼容。片内含有8位中央处理器和闪烁存储单元，功能强大AT89C51单片机可为您提供许多高性价比的应用场合，可灵活应用于各种控制领域。
主要性能参数：
·与MCS-51产品指令系统完全兼容
·4K字节可重擦写Flash闪速存储器
·1000次擦写周期
·数据保留时间：10年
·全静态操作：0Hz—24MHz
·三级加密程序存储器
·128×8字节内部RAM
·32个可编程I/O口线
·2个16位定时/计数器
·6个中断源
·可编程串行UART通道
·低功耗空闲和掉电模式
·片内振荡器和时钟电路
·全双工UART串行中断口线
·双数据寄存器指针
功能特性概述：
AT89C51提供以下标准功能：4K字节Flash闪速存储器，128字节内部RAM，32个I/O口线，两个16位定时/计数器，一个5向量两级中断结构，一个全双工串行通信口，片内振荡器及时钟电路。同时，AT89C51可降至0Hz的静态逻辑操作，并支持两种软件可选的节电工作模式。空闲方式停止CPU的工作，但允许RAM，定时/计数器。串行通信口及中断系统继续工作。掉电方式保存RAM中的内容，但振荡器停止工作并禁止其它所有部件工作直到下一个硬件复位。
AT89C51单片机是一个行业标准架构，被广泛接受和应用，并作为一种开发工具。有许多工业供应商，他们供应这种控制器或把这种控制器集成到某种类型的系统芯片的结构。医学研究理事会和高级微电子研究所都选择这个设备，但他们论证的是两种截然不同固化工艺。医学研究理事会的实例是使用时间锁存，需要具体时间以确保单
粒子效应减少到最低限度。高级微电子研究所采用超低功耗，以及布局和建筑固化工艺的设计原则来实现其结果。这些是与Aeroflex联合技术微电子中心（ UTMC ）完全不同的方法，抗辐射固化的AT89C51的工业供应商，利用抗辐射固化进程研制自己的AT89C51单片机。
引脚功能说明：
·V
：电源电压
CC
·GND：地
·P0口：P0口是一组8位漏极开路型双向I/O口，也即地址/数据总线复用口。作为输出口用时，每位能吸收电流的方式驱动8个TTL逻辑门电路，对端口写“1”可作为高阻抗输入端用。
在访问外部数据存储器或程序存储器时，这组口线分时转换地址（低8位）和数据总线复用，在访问期间即或内部上拉电阻。
在Flash编程时，P0口接收指令字节，而在程序校验时，输出指令字节，校验时，要求外接上拉电阻。
·P1口：P1是一个带有内部上拉电阻的8位双向I/O口，P1的输出缓冲级可驱动（吸收或输出电流）4个TTL逻辑门电路。对端口写“1”，通过内部的上拉电阻把端口拉到高电平，此时可作输入口。作输入口使用时，因为内部存在上拉电阻，某个
）。
引脚被外部信号拉低时会输出一个电流（I
IL
Flash编程和程序校验期间，P1接收低8位地址。
·P2口：P2是一个带有内部上拉电阻的8位双向I/O口，P2的输出缓冲级可驱动（吸收或输出电流）4个TTL逻辑门电路。对端口写“1”，通过内部的上拉电阻把端口拉到高电平，此时可作输入口。作输入口使用时，因为内部存在上拉电阻，某个
）。
引脚被外部信号拉低时会输出一个电流（I
IL
在访问外部程序存储器或16位地址的外部数据存储器（例如执行MOVX@DPTR指令）时，P2口送出高8位地址数据。在访问8位地址的外部数据存储器（如执行MOVX@RI 指令）时，P2口线上的内容在整个访问期间不改变。
Flash编程或检验时，P2亦接收高位地址和其它控制信号。
·P3口：P3口是一组带有内部电阻的8位双向I/O口，P3口输出缓冲故可驱动4个TTL电路。当P3口写入“1”后，它们被内部上拉为高电平，并用作输入。作为输入，由于外部下拉为低电平，P3口将输出电流（ILL）这是由于上拉的缘故。
P3口除了作为一般的I/O口外，更重要的用途是它的第二功能，如表1所示：
表1 P3口第二功能
端口引脚第二功能
P3口还接收一些用于闪烁存储器编程和程序校验的控制信号。
·RET ：复位输入。当振荡器工作时，RET 引脚出现两个机器周期以上高电平将使单片机复位。
·ALE/PROG ：当访问外部程序存储器或数据存储器时，ALE （地址锁存允许）输出脉冲用于锁存地址的低8位字节。对Flash 存储器编程期间，该引脚还用于输入编程脉冲（PROG ）。即使不访问外部存储器，ALE 仍以时钟振荡频率的1/6输出固定的正脉冲信号，因此它可对外输出时钟或用于定时目的。要注意的是：每当访问外部数据存储器时将跳过一个ALE 脉冲。
如有必要，可通过对特殊功能寄存器（SFR ）区中的8EH 单元的D0位置位，可禁止ALE 操作。该位置位后，只有一条MOVX 和MOVC 指令ALE 才会被激活。此外，该引脚会被微弱拉高，单片机执行外部程序时，应设置ALE 无效。 ·PSEN ：程序储存允许（PSEN ）输出是外部程序存储器的读选通信号，当AT89C51由外部程序存储器取指令（或数据）时，每个机器周期两次PSEN 有效，即输出两个脉冲。在此期间，当访问外部数据存储器，这两次有效的PSEN 信号不出现。
EA /VPP ：外部访问允许。欲使CPU 仅访问外部程序存储器（地址为0000H —FFFFH ），EA 端必须保持低电平（接地）。需注意的是：如果加密位LB1被编程，复位时内部会锁存EA 端状态。如EA 端为高电平（接VCC 端），CPU 则执行内部程序存储器中的指令。当EA 保持低电平时，则在此期间外部程序存储器（0000H-FFFFH ），不管是否有内部程序存储器。
Flash 存储器编程时，该引脚加上+12V 的编程允许电源V PP ，当然这必须是该器
件是使用12V 编程电压V PP 。
XTAL1：振荡器反相放大器及内部时钟发生器的输入端。
XTAL2：振荡器反相放大器的输出端。 Ready/BUSY ：字节编程的进度可通过RDY/BSY 输出信号监测，编程期间，ALE 变为高电平“H ”后P3.4（RDY/BSY ）端电平被拉低，表示正在编程状态（忙状态）。编程完成后，P3.4变为高电平表示准备就绪状态。 P3.0
RXD P3.1
TXD P3.2
INT0 P3.3
INT1 P3.4
T0 P3.5
T1 P3.6
WR P3.7 RD
振荡器特性：
XTAL1和XTAL2分别为反向放大器的输入和输出。该反向放大器可以配置为片内振荡器。石晶振荡和陶瓷振荡均可采用。如采用外部时钟源驱动器件，XTAL2应不接。有余输入至内部时钟信号要通过一个二分频触发器，因此对外部时钟信号的脉宽无任何要求，但必须保证脉冲的高低电平要求的宽度。
时钟振荡器：
AT89C51中有一个用于构成内部振荡器的高增益反相放大器，引脚XTAL1和XTAL2分别是该放大器的输入端和输出端。这个放大器与作为反馈元件的片外石英晶体或陶瓷谐振器一起构成自激振荡器。
用户也可以采用外部时钟。这种情况下，外部时钟脉冲接到XTAL1端，即内部时钟发生器的输入端，XTAL2则悬空。
由于外部时钟信号是通过一个2分频触发器后作为内部时钟信号的，所以对外部时钟信号的占空比没有特殊要求，但最小高电平持续时间和最大的低电平持续时间应符合产品技术条件的要求。
空闲节电模式：
在空闲工作模式状态，CPU保持睡眠状态而所有片内的外设仍保持激活状态，这种方式由软件产生。此时，片内RAM和所有特殊功能寄存器的内容保持不变。空闲模式可由任何允许的中断请求或硬件复位终止。
通过硬件复位也可将空闲工作模式终止。需要注意的是：当由硬件复位来终止空闲工作模式时，CPU通常是从激活空闲模式那条指令的下一条指令开始继续执行程序的，要完成内部复位操作，硬件复位脉冲要保持两个机器周期有效，在这种情况下，内部禁止CPU访问片内RAM，而允许访问其它端口。为了避免可能对端口产生意外写入，激活空闲模式的那条指令后一条指令不应是一条对端口或外部存储器的写入指令。
掉电模式：
在掉电模式下，振荡器停止工作，进入掉电模式的指令是最后一条被执行的指令，片内RAM和特殊功能寄存器的内容在终止掉电模式前被冻结。退出掉电模式的唯一方法是硬件复位，复位后将重新定义全部特殊功能寄存器但不改变RAM中的内容，在恢复到正常工作电平前，复位应无效，且必须保持一定时间以使振荡器重启动并V
CC
稳定工作。
Flash闪速存储器的编程：
AT89C51单片机内部有4K字节的Flash PEROM，这个Flash存储阵列出厂时已处于擦除状态（即所有存储单元的内容均为FFH），用户随时可对其进行编程。编程接口可接收高电压（+12V）或低电压（V
）的允许编程信号。低电压编程模式适合于用
CC
户在线编程系统，而高电压编程模式可与通用EPROM编程器兼容。
AT89C51的程序存储器阵列是采用字节写入方式编程的，每次写入一个字节，要对整个芯片内的PEROM程序存储器写入一个非空字节，必须使用片擦除的方式将整个存储器的内容清除。
编程方法：
编程前，须根据表设置好地址、数据及控制信号。AT89C51编程方法如下：
1、在地址线上加上要编程单元的地址信号。
2、在数据线上加上要写入的数据字节。
3、激活相应的控制信号。
端加上+12V编程电压。
4、在高电压编程方式时，将EA/V
PP
5、每对Flash存储阵列写入一个字节或每写入一个程序加密位，加上一个ALE/PROG编程脉冲。改变编程单元的地址和写入的数据，重复1—5步骤，直到全部文件编程结束。每个字节写入周期是自身定时的，通常约为1.5ms。
数据查询：
AT89C51单片机用数据查询方式来检测一个写周期是否结束，在一个写周期中，如需读取最后写入的那个字节，则读出的数据最高位是原来写入字节最高位的反码。写周期完成后，有效的数据就会出现在所有输出端上，此时，可进入下一个字节的写周期，写周期开始后，可在任意时刻进行数据查询。
程序校验：
如果加密位LB1、LB2没有进行编程，则代码数据可通过地址和数据线读回原编写的数据。加密位不可直接校验，加密位的校验可通过对存储器的校验和写入状态来验证。
芯片擦除：
整个PEROM阵列和三个锁定位的电擦除可通过正确的控制信号组合，并保持ALE 管脚处于低电平10ms 来完成。在芯片擦操作中，代码阵列全被写“1”且在任何非空存储字节被重复编程以前，该操作必须被执行。
此外，AT89C51设有稳态逻辑，可以在低到零频率的条件下静态逻辑，支持两种软件可选的掉电模式。在闲置模式下，CPU停止工作。但RAM，定时器，计数器，串口和中断系统仍在工作。在掉电模式下，保存RAM的内容并且冻结振荡器，禁止所用其他芯片功能，直到下一个硬件复位为止。
读片内签名字节：
读签名字节的过程和单元030H、031H及032H的正常校验相仿，只需将P3.6和P3.7保持低电平，返回值意义如下：
(030H)=1EH声明产品由ATMEL公司制造
(031H)=51H声明为AT89C51单片机
(032H)=FFH声明为12V编程电压
(032H)=05H声明为5V编程电压
编程接口：
采用控制信号的正确组合可对Flash闪速存储阵列中的每一代码字节进行写入和存储器的整片擦除，写操作周期是自身定时的，初始化后它将自动定时到操作完成。看门狗（WDT）电路：
看门狗（WDT）电路的主要是实现复位功能。当单片机运行出现死循环时,看门狗（WDT）电路可以起保护功能,实现复位作用。
Introduction of AT89C51
Description:
The AT89C51 is a low-power, high-performance CMOS 8-bit microcomputer with 4K bytes of Flash programmable and erasable read only memory (PEROM). The device is manufactured using Atmel’s high-density nonvolatile memory technology and is compatible with the industry-standard MCS-51 instruction set and pinout. The on-chip Flash allows the program memory to be reprogrammed in-system or by a conventional nonvolatile memory programmer. By combining a versatile 8-bit CPU with Flash on a monolithi c chip, the ATMEL Co.’s AT89C51 is a powerful microcomputer which provides a highly-flexible and cost-effective solution to many embedded control applications. Features:
·Compatible with instruction set of MCS-51 products
·4K bytes of in-system reprogrammable Flash memory
·Endurance: 1000 write/erase cycles
·Data retention time: 10 years
·Fully static operation: 0 Hz to 24 MHz
·Three-level program memory lock
·128×8-bit internal RAM
·32 programmable I/O lines
·Two 16-bit Timer/Counters
·Six interrupt source
·Programmable serial channel
·Low-power idle and Power-down modes
·On-chip oscillator and clock circuitry
·Full-duplex UART serial port interrupt line
·Dual Data Pointer Register
Function Characteristic Description:
The AT89C51 provides the following standard features: 4K bytes of Flash memory, 128 bytes of RAM, 32 I/O lines, two 16-bit timer/counters, a five vector two-level interrupt architecture, a full duplex serial port, on-chip oscillator and clock circuitry. In addition, the AT89C51 is designed with static logic for operation down to zero frequency and supports two software selectable power saving modes. The Idle Mode stops the CPU while allowing the RAM, timer/counters, serial port and interrupt system to continue functioning. The Power-down Mode saves the RAM contents but freezes the oscillator disabling all other chip functions until the next hardware reset.
The 8051 microcontroller is an industry standard architecture that has broad acceptance, wide-ranging applications and development tools available. There are numerous commercial vendors that supply this controller or have it integrated into some type of system-on-a-chip structure. Both MRC and IAμE chose this device to demonstrate two distinctly different technologies for hardening. The MRC example of this is to use temporal latches that require specific timing to ensure that single event effects are minimized. The IAμE technology uses ultra low power, and layout and architecture HBD design rules to achieve their results. These are fundamentally different than the approach by Aeroflex-United Technologies Microelectronics Center (UTMC), the commercial vendor of a radiation– hardened 8051, that built their 8051 microcontroller using radiation hardened processes. This broad range of technology within one device structure makes the 8051an ideal vehicle for performing this technology evaluation
Pin Description:
·VCC: Supply voltage
·GND: Ground
·Port 0: Port 0 is an 8-bit open-drain bi-directional I/O port. As an output port, each pin can sink eight TTL inputs. When 1s are written to port 0 pins, the pins can be used as high impedance inputs.
Port 0 may also be configured to be the multiplexed low order address/bus during accesses to external program and data memory. In this mode P0 has internal pull ups.
Port 0 also receives the code bytes during Flash programming, and outputs the code bytes during program verification. External pull ups are required during program
verification.
·Port 1: Port 1 is an 8-bit bidirectional I/O port with internal pull ups. The Port 1 output buffers can sink/source four TTL inputs. When 1s are written to Port 1 pins they are pulled high by the internal pull ups and can be used as inputs. As inputs, Port 1 pins that are externally being pulled low will source current (IIL) because of the internal pull ups.
Port 1 also receives the low-order address bytes during Flash programming and verification.
·Port 2: Port 2 is an 8-bit bi-directional I/O port with internal pull ups. The Port 2 output buffers can sink/source four TTL inputs. When 1s are written to Port 2 pins they are pulled high by the internal pull ups and can be used as inputs. As inputs, Port 2 pins that are externally being pulled low will source current (IIL) because of the internal pull ups.
Port 2 emits the high-order address byte during fetches from external program memory and during accesses to external data memory which uses 16-bit addresses (MOVX @ DPTR). In this application, it uses strong internal pull ups when emitting 1s. During accesses to external data memory which uses 8-bit addresses (MOVX @ RI). Port 2 emits the contents of the P2 Special Function Register.
Port 2 also receives the high-order address bits and some control signals during Flash programming and verification.
·Port 3: Port 3 is an 8-bit bi-directional I/O port with internal pullups.The Port 3 output buffers can sink/source four TTL inputs. When the P3 I write "1" after, they are internal pull-up is high, and used as input. As input, due to the external pull-down for the low, P3 port output current (ILL) This is due to pull-up's sake.
Port 3 also serves the functions of various special features of the AT89C51 as listed below:
Port 3 also receives some control signals for Flash programming and verification.
·RST: Reset input. A high on this pin for two machine cycles while the oscillator is running resets the device.
·ALE/PROG: Address Latch Enable output pulse for latching the low byte of the address during accesses to external memory. This pin is also the program pulse input (PROG) during Flash programming. In normal operation ALE is emitted at a constant rate of 1/6 the oscillator frequency, and may be used for external timing or clocking purposes. Note, however, that one ALE pulse is skipped during each access to external Data Memory.
If desired, ALE operation can be disabled by setting bit 0 of SFR location 8EH. With the bit set, ALE is active only during a MOVX or MOVC instruction. Otherwise, the pin is weakly pulled high. Setting the ALE-disable bit has no effect if the microcontroller is in external execution mode.
·PSEN：Program Store Enable is the read strobe to external program memory. When the AT89C51 is executing code from external program memory, PSEN is activated twice each machine cycle, except that two PSEN activations are skipped during each access to external data memory.
·/ EA /VPP：External Access Enable. EA must be strapped to GND in order to enable the device to fetch code from external program memory locations starting at 0000H up to FFFFH. Note, however, that if lock bit 1 is programmed, EA will be internally latched on reset. EA should be strapped to VCC for internal program executions. When / EA to maintain low, then during this period the external program memory (0000H-FFFFH), regardless of whether an internal program memory.
This pin also receives the 12-volt programming enable voltage (VPP) during Flash programming, for parts that require 12-volt VPP.
·XTAL1：Input to the inverting oscillator amplifier and input to the internal clock operating circuit.
·XTAL2：Output from the inverting oscillator amplifier.
·Ready/BUSY: The progress of byte programming can also be monitored by the RDY/BSY output signal. P3.4 is pulled low after ALE goes high during programming to indicate BUSY. P3.4 is pulled high again when programming is done to indicate READY. Oscillator Characteristics：
XTAL1 and XTAL2 respectively, reverse amplifier input and output. The reverse amplifier can be configured as on-chip oscillator. Shi Jing oscillation and ceramic oscillation can be used. If using an external clock source drive the device, XTAL2 should
not take. More than input to the internal clock signal through a two-way flip-flop, so the external clock signal pulse width without any request, but must ensure that the high-low pulse width requirements.
Clock Oscillator：
XTAL1 and XTAL2 are the input and output, respectively, of an inverting amplifier which can be configured for use as an on-chip oscillator. Either a quartz crystal or ceramic resonator may be used.
To drive the device from an external clock source, XTAL2 should be left unconnected while XTAL1 is driven.
There are no requirements on the duty cycle of the external clock signal, since the input to the internal clocking circuitry is through a divide by two flip trigger, but minimum and maximum voltage high and low time specifications must be observed.
Idle Mode：
In idle mode, the CPU puts itself to sleep while all the on-chip peripherals remain active. The mode is invoked by software. The content of the on-chip RAM and all the special functions registers remain unchanged during this mode. The idle mode can be terminated by any enabled interrupt or by a hardware reset.
It should be noted that when idle is terminated by a hardware reset, the device normally resumes program execution, from where it left off, up to two machine cycles before the internal reset algorithm takes control. On-chip hardware inhibits access to internal RAM in this event, but access to the port pins is not inhibited. To eliminate the possibility of an unexpected write to a port pin when Idle is terminated by reset, the instruction following the one that invokes Idle should not be one that writes to a port pin or to external memory.
Power-down Mode:
In the power-down mode, the oscillator is stopped, and the instruction that invokes power-down is the last instruction executed. The on-chip RAM and special function registers retain their values until the power-down mode is terminated. The only exit from power-down is a hardware reset. Reset redefines the special function registers but does not change the on-chip RAM. The reset should not be activated before VCC is restored to its normal operating level and must be held active long enough to allow the oscillator to restart and stabilize.
Programming the Flash:
The AT89C51 is normally shipped with the on-chip Flash memory array in the erased state (that is, contents = FFH) and ready to be programmed. The programming
interface accepts either a high-voltage (12-volt) or a low-voltage (VCC) program enable signal. The low-voltage programming mode provides a convenient way to program the AT89C51 inside the user’s system, while th e high-voltage programming mode is compatible with conventional third party Flash or EPROM programmers.The AT89C51 is shipped with either the high-voltage or low-voltage programming mode enabled.
The AT89C51 code memory array is programmed byte-by-byte in either programming mode. To program any nonblank byte in the on-chip Flash memory, the entire memory must be erased using the chip erase mode.
Programming Algorithm:
Before programming the AT89C51, the address, data and control signals should be set up according to the Flash programming mode table .To program the AT89C51, take the following steps:
1. Input the desired memory location on the address lines.
2. Input the appropriate data byte on the data lines.
3. Activate the correct combination of control signals.
4. Raise EA/VPP to 12V for the high-voltage programming mode.
5. Pulse ALE/PROG once to program a byte in the Flash array or the lock bits.
The byte-write cycle is self-timed and typically takes no more than 1.5ms. Repeat steps 1 through 5, changing the address and data for the entire array or until the end of the object file is reached.
Data Polling:
The AT89C51 features Data Polling to indicate the end of a write cycle. During a write cycle, an attempted read of the last byte written will result in the complement of the written datum on PO.7. Once the write cycle has been completed, true data are valid on all outputs, and the next cycle may begin. Data polling may begin any time after a write cycle has been initiated.
Program Verify:
If lock bits LB1 and LB2 have not been programmed, the programmed code data can be read back via the address and data lines for verification. The lock bits cannot be verified directly. Verification of the lock bits is achieved by observing that their features are enabled.
Chip Erase:
The whole array and three lock-bit PEROM electrical erase control signals through the right combination and maintain ALE pin is low 10ms to complete. Cleaning operation in the chip, code arrays were all written "1" and in any non-empty memory byte has been
programmed to repeat the past, the operation must be executed. In addition, AT89C51 with steady-state logic, and can be in the low to zero frequency under the conditions of static logic, and supports two software selectable power-down mode. In idle mode, CPU stop working. But the RAM, timers, counters, serial port and interrupt system are still working. In the power-down mode, to save the contents of RAM and a freeze oscillator, to prohibit the use of other chip functions until the next until a hardware reset.
Reading the Signature Bytes:
The signature bytes are read by the same procedure as a normal verification of locations 030H, 031H, and 032H, except that P3.6 and P3.7 must be pulled to a logic low. The values returned are as follows:
(030H) = 1EH indicates manufactured by ATMEL
(031H) = 51H indicates AT89C51 single-chip
(032H) = FFH indicates 12V programming
(032H) = 05H indicates 5V programming
Programming Interface:
Every code byte in the Flash array can be written and the entire array can be erased by using the appropriate combination of control signals. The write operation cycle is self timed and once initiated, will automatically time itself to completion.
Watchdog (WDT) circuit:
Watchdog (WDT) reset circuit is to achieve the main functionality. When the MCU is running an infinite loop occurs when the watchdog (WDT) can play a protection circuit to achieve reduction effect.
外文翻译
Load and Ultimate Moment of Prestressed Concrete Action Under Overload-Cracking Load It has been shown that a variation in the external load acting on a prestressed beam results in a change in the location of the pressure line for beams in the elastic range.This is a fundamental principle of prestressed construction.In a normal prestressed beam,this shift in the location of the pressure line continues at a relatively uniform rate,as the external load is increased,to the point where cracks develop in the tension fiber.After the cracking load has been exceeded,the rate of movement in the pressure line decreases as additional load is applied,and a significant increase in the stress in the prestressing tendon and the resultant concrete force begins to take place.This change in the action of the internal moment continues until all movement of the pressure line ceases.The moment caused by loads that are applied thereafter is offset entirely by a corresponding and proportional change in the internal forces,just as in reinforced-concrete construction.This fact,that the load in the elastic range and the plastic range is carried by actions that are fundamentally different,is very significant and renders strength computations essential for all designs in order to ensure that adequate safety factors exist.This is true even though the stresses in the elastic range may conform to a recognized elastic design criterion. It should be noted that the load deflection curve is close to a straight line up to the cracking load and that the curve becomes progressively more curved as the load is increased above the cracking load.The curvature of the load-deflection curve for loads over the cracking load is due to the change in the basic internal resisting moment action that counteracts the applied loads,as described above,as well as to plastic strains that begin to take place in the steel and the concrete when stressed to high levels. In some structures it may be essential that the flexural members remain crack free even under significant overloads.This may be due to the structures’being exposed to exceptionally corrosive atmospheres during their useful life.In designing prestressed members to be used in special structures of this type,it may be necessary to compute the load that causes cracking of the tensile flange,in order to ensure that adequate safety against cracking is provided by the design.The computation of the moment that will cause cracking is also necessary to ensure compliance with some design criteria. Many tests have demonstrated that the load-deflection curves of prestressed beams are approximately linear up to and slightly in excess of the load that causes the first cracks in the tensile flange.(The linearity is a function of the rate at which the load is applied.)For this reason,normal elastic-design relationships can be used in computing the cracking load by simply determining the load that results in a net tensile stress in the tensile flange(prestress minus the effects of the applied loads)that is equal to the tensile strength of the concrete.It is customary to assume that the flexural tensile strength of the concrete is equal to the modulus of rupture of the
毕业设计外文翻译资料
外文出处： 《Exploiting Software How to Break Code》By Greg Hoglund, Gary McGraw Publisher : Addison Wesley Pub Date : February 17, 2004 ISBN : 0-201-78695-8 译文标题： JDBC接口技术 译文： JDBC是一种可用于执行SQL语句的JavaAPI（ApplicationProgrammingInterface应用程序设计接口）。它由一些Java语言编写的类和界面组成。JDBC为数据库应用开发人员、数据库前台工具开发人员提供了一种标准的应用程序设计接口，使开发人员可以用纯Java语言编写完整的数据库应用程序。 一、ODBC到JDBC的发展历程 说到JDBC，很容易让人联想到另一个十分熟悉的字眼“ODBC”。它们之间有没有联系呢？如果有，那么它们之间又是怎样的关系呢？ ODBC是OpenDatabaseConnectivity的英文简写。它是一种用来在相关或不相关的数据库管理系统（DBMS）中存取数据的，用C语言实现的，标准应用程序数据接口。通过ODBCAPI，应用程序可以存取保存在多种不同数据库管理系统（DBMS）中的数据，而不论每个DBMS使用了何种数据存储格式和编程接口。 1．ODBC的结构模型 ODBC的结构包括四个主要部分：应用程序接口、驱动器管理器、数据库驱动器和数据源。应用程序接口：屏蔽不同的ODBC数据库驱动器之间函数调用的差别，为用户提供统一的SQL编程接口。 驱动器管理器：为应用程序装载数据库驱动器。 数据库驱动器：实现ODBC的函数调用，提供对特定数据源的SQL请求。如果需要，数据库驱动器将修改应用程序的请求，使得请求符合相关的DBMS所支持的文法。 数据源：由用户想要存取的数据以及与它相关的操作系统、DBMS和用于访问DBMS的网络平台组成。 虽然ODBC驱动器管理器的主要目的是加载数据库驱动器，以便ODBC函数调用，但是数据库驱动器本身也执行ODBC函数调用，并与数据库相互配合。因此当应用系统发出调用与数据源进行连接时，数据库驱动器能管理通信协议。当建立起与数据源的连接时，数据库驱动器便能处理应用系统向DBMS发出的请求，对分析或发自数据源的设计进行必要的翻译，并将结果返回给应用系统。 2．JDBC的诞生 自从Java语言于1995年5月正式公布以来，Java风靡全球。出现大量的用java语言编写的程序，其中也包括数据库应用程序。由于没有一个Java语言的API，编程人员不得不在Java程序中加入C语言的ODBC函数调用。这就使很多Java的优秀特性无法充分发挥，比如平台无关性、面向对象特性等。随着越来越多的编程人员对Java语言的日益喜爱，越来越多的公司在Java程序开发上投入的精力日益增加，对java语言接口的访问数据库的API 的要求越来越强烈。也由于ODBC的有其不足之处，比如它并不容易使用，没有面向对象的特性等等，SUN公司决定开发一Java语言为接口的数据库应用程序开发接口。在JDK1．x 版本中，JDBC只是一个可选部件，到了JDK1．1公布时，SQL类包（也就是JDBCAPI）
1外文文献翻译原文及译文汇总
华北电力大学科技学院 毕业设计（论文）附件 外文文献翻译 学号：121912020115姓名：彭钰钊 所在系别：动力工程系专业班级：测控技术与仪器12K1指导教师：李冰 原文标题：Infrared Remote Control System Abstract 2016 年 4 月 19 日
红外遥控系统 摘要 红外数据通信技术是目前在世界范围内被广泛使用的一种无线连接技术，被众多的硬件和软件平台所支持。红外收发器产品具有成本低，小型化，传输速率快，点对点安全传输，不受电磁干扰等特点，可以实现信息在不同产品之间快速、方便、安全地交换与传送，在短距离无线传输方面拥有十分明显的优势。红外遥控收发系统的设计在具有很高的实用价值，目前红外收发器产品在可携式产品中的应用潜力很大。全世界约有1亿5千万台设备采用红外技术，在电子产品和工业设备、医疗设备等领域广泛使用。绝大多数笔记本电脑和手机都配置红外收发器接口。随着红外数据传输技术更加成熟、成本下降，红外收发器在短距离通讯领域必将得到更广泛的应用。 本系统的设计目的是用红外线作为传输媒质来传输用户的操作信息并由接收电路解调出原始信号，主要用到编码芯片和解码芯片对信号进行调制与解调，其中编码芯片用的是台湾生产的PT2262，解码芯片是PT2272。主要工作原理是：利用编码键盘可以为PT2262提供的输入信息，PT2262对输入的信息进行编码并加载到38KHZ的载波上并调制红外发射二极管并辐射到空间，然后再由接收系统接收到发射的信号并解调出原始信息，由PT2272对原信号进行解码以驱动相应的电路完成用户的操作要求。 关键字：红外线；编码；解码；LM386；红外收发器。 1 绪论
计算机网络安全文献综述
计算机网络安全综述学生姓名：李嘉伟 学号：11209080279 院系：信息工程学院指导教师姓名：夏峰二零一三年十月
［摘要］ 随着计算机网络技术的快速发展，网络安全日益成为人们关注的焦点。本文分析了影响网络安全的主要因素及攻击的主要方式，从管理和技术两方面就加强计算机网络安全提出了针对性的建议。 ［关键词］ 计算机网络；安全；管理；技术；加密；防火墙 一．引言 计算机网络是一个开放和自由的空间，但公开化的网络平台为非法入侵者提供了可乘之机，黑客和反黑客、破坏和反破坏的斗争愈演愈烈，不仅影响了网络稳定运行和用户的正常使用，造成重大经济损失，而且还可能威胁到国家安全。如何更有效地保护重要的信息数据、提高计算机网络的安全性已经成为影响一个国家的政治、经济、军事和人民生活的重大关键问题。本文通过深入分析网络安全面临的挑战及攻击的主要方式，从管理和技术两方面就加强计算机网络安全提出针对性建议。
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建筑类外文文献及中文翻译
forced concrete structure reinforced with an overviewRein Since the reform and opening up, with the national economy's rapid and sustained development of a reinforced concrete structure built, reinforced with the development of technology has been great. Therefore, to promote the use of advanced technology reinforced connecting to improve project quality and speed up the pace of construction, improve labor productivity, reduce costs, and is of great significance. Reinforced steel bars connecting technologies can be divided into two broad categories linking welding machinery and steel. There are six types of welding steel welding methods, and some apply to the prefabricated plant, and some apply to the construction site, some of both apply. There are three types of machinery commonly used reinforcement linking method primarily applicable to the construction site. Ways has its own characteristics and different application, and in the continuous development and improvement. In actual production, should be based on specific conditions of work, working environment and technical requirements, the choice of suitable methods to achieve the best overall efficiency. 1、steel mechanical link 1.1 radial squeeze link Will be a steel sleeve in two sets to the highly-reinforced Department with superhigh pressure hydraulic equipment (squeeze tongs) along steel sleeve radial squeeze steel casing, in squeezing out tongs squeeze pressure role of a steel sleeve plasticity deformation closely integrated with reinforced through reinforced steel sleeve and Wang Liang's Position will be two solid steel bars linked Characteristic: Connect intensity to be high, performance reliable, can bear high stress draw and pigeonhole the load and tired load repeatedly.
外文翻译
Journal of Industrial Textiles https://www.wendangku.net/doc/da8277088.html,/ Optimization of Parameters for the Production of Needlepunched Nonwoven Geotextiles Amit Rawal, Subhash Anand and Tahir Shah 2008 37: 341Journal of Industrial Textiles DOI: 10.1177/1528083707081594 The online version of this article can be found at: https://www.wendangku.net/doc/da8277088.html,/content/37/4/341 Published by: https://www.wendangku.net/doc/da8277088.html, can be found at:Journal of Industrial TextilesAdditional services and information for https://www.wendangku.net/doc/da8277088.html,/cgi/alertsEmail Alerts: https://www.wendangku.net/doc/da8277088.html,/subscriptionsSubscriptions: https://www.wendangku.net/doc/da8277088.html,/journalsReprints.navReprints: https://www.wendangku.net/doc/da8277088.html,/journalsPermissions.navPermissions: https://www.wendangku.net/doc/da8277088.html,/content/37/4/341.refs.htmlCitations: - Mar 28, 2008Version of Record >>
毕业设计外文翻译附原文
外文翻译 专业机械设计制造及其自动化学生姓名刘链柱 班级机制111 学号1110101102 指导教师葛友华
外文资料名称： Design and performance evaluation of vacuum cleaners using cyclone technology 外文资料出处：Korean J. Chem. Eng., 23(6), (用外文写) 925-930 (2006) 附件： 1.外文资料翻译译文 2.外文原文
应用旋风技术真空吸尘器的设计和性能介绍 吉尔泰金，洪城铱昌，宰瑾李， 刘链柱译 摘要：旋风型分离器技术用于真空吸尘器 - 轴向进流旋风和切向进气道流旋风有效地收集粉尘和降低压力降已被实验研究。优化设计等因素作为集尘效率，压降，并切成尺寸被粒度对应于分级收集的50％的效率进行了研究。颗粒切成大小降低入口面积，体直径，减小涡取景器直径的旋风。切向入口的双流量气旋具有良好的性能考虑的350毫米汞柱的低压降和为1.5μm的质量中位直径在1米3的流量的截止尺寸。一使用切向入口的双流量旋风吸尘器示出了势是一种有效的方法，用于收集在家庭中产生的粉尘。 摘要及关键词：吸尘器; 粉尘; 旋风分离器 引言 我们这个时代的很大一部分都花在了房子，工作场所，或其他建筑，因此，室内空间应该是既舒适情绪和卫生。但室内空气中含有超过室外空气因气密性的二次污染物，毒物，食品气味。这是通过使用产生在建筑中的新材料和设备。真空吸尘器为代表的家电去除有害物质从地板到地毯所用的商用真空吸尘器房子由纸过滤，预过滤器和排气过滤器通过洁净的空气排放到大气中。虽然真空吸尘器是方便在使用中，吸入压力下降说唱空转成比例地清洗的时间，以及纸过滤器也应定期更换，由于压力下降，气味和细菌通过纸过滤器内的残留粉尘。 图1示出了大气气溶胶的粒度分布通常是双峰形，在粗颗粒（>2.0微米）模式为主要的外部来源，如风吹尘，海盐喷雾，火山，从工厂直接排放和车辆废气排放，以及那些在细颗粒模式包括燃烧或光化学反应。表1显示模式，典型的大气航空的直径和质量浓度溶胶被许多研究者测量。精细模式在0.18?0.36 在5.7到25微米尺寸范围微米尺寸范围。质量浓度为2?205微克，可直接在大气气溶胶和 3.85至36.3μg/m3柴油气溶胶。
外文翻译1
译文（一） THE ACCOUNTING REVIEW V ol. 83, No. 3 2008 pp. 823–853 市场参与者的杜邦分析的使用 马克?t?Soliman 华盛顿大学 文摘:杜邦分析,一种常见的财务报表分析，依靠于净营业资产收益率的两个乘法组件:利润率和资产周转率。这两个会计比率衡量不同的构造。因此,有不同的属性。之前的研究已经发现,资产周转率的变化是未来收益的变化正相关。本文全面探讨了杜邦组件和沿着三个维度有助于文学。首先,本文有助于财务报表分析文献,发现在这个会计信息信号实际上是增量学习会计信号在先前的研究在预测未来收益。其次,它有助于文学在股票市场上使用的会计信息通过检查眼前和未来的股本回报投资者应对这些组件。最后,它增加了分析师的文献处理会计信息的再次测试直接和延迟反应的分析师通过同期预测修正以及未来预测错误。一致的跨市场加入者的两组,结果表明是有用的信息就是明证杜邦组件和股票收益之间的联系以及维度分析师预测。然而,我发现预测未来预测错误和异常返回信息处理表明似乎没有完成。平均水平,分析表明杜邦组件代表增量和可行的操作特征信息的公司。 关键词:财务报表分析、杜邦分析、市场回报、分析师预估。 数据可用性:在这项研究中使用的数据是公开的来源显示的文本。 在本文中,我分析杜邦分析中包含的信息是否与股市回报相关和分析师预测。之前的研究文档组件从杜邦分析,分解的净营业资产收益率为利润率和资产周转率,有解释力对未来盈利能力的变化。本文增加了文献综合研究投资者和分析师反应杜邦组件三个维度。首先,它复制先前记录的预测能力和检查是否健壮和增量其他预测已经考虑在文学的存在。其次,它探讨了使用这些组件的股市投资者通过观察同生和未来收益。在同时代的长窗协会和短时期限信息测试,结果显示积极联系杜邦组件和股本回报率。但小未来异常返回交易策略显示的信息可能不完整的处理。最后,检查当前预测修正由卖方分析师和未来的预测错误。尽管他们似乎修改他们的预测未来收益与这些杜邦组件中的信息一致,修订似乎不完整就是明证可预测的未来预测错误。一致的市场参与者,在两组同期结果表明,信息是有用的,但是未来的测试表明,信息处理似乎没有完成。 由金矿和笔者(2001)提供了一个使用剩余收益的股票估值方法框架,给出了一个简单的财务比率分析的直接映射到股票估值。特别是他们用杜邦分析,分解公司的净营业资产收益率(RNOA)利润率(PM)和资产周转率(ATO)点的地方1。PM和ATO会计信号,测量不同结构对一个公司的业务2。PM 往往是来自定价权,如产品创新,产品定位,品牌知名度,先发优势和市场定位。ATO措施资产利用率和效率,通常来自于有效的利用财产,工厂和设备,有效的库存流程;和其他形式的资本管理工作3。 我们有理由期待竞争力量的影响这两个来源盈利能力不同。大的利润率通常吸引新进入者进入市场或快速模仿新思想从现有的竞争对手。由此产生的竞争导致高利润率回归正常水平,暗示更多暂时的利益。与利润不同,然而,竞争可能少威胁要部署一个有效的资产。更难以模仿另一个公司的高效生产流程因为这样模仿通常包括大型和昂贵的改革目前的工厂和操作。 1.具体来说,RNOA营业收入/平均净营业资产,PM营业收入/销售和ATO销售 /平均净营业资产。此后,点和ATO被称为“杜邦公司组成”。另一个常见的形式是分解罗伊(利润杠杆资产周转率)或(NI /产品销售/资产资产/股本)。讨论的“估值理论和RNOA”部分,我在分析使用RNOA为了专注于操作,因此抽象从公司的融资决策。 2.例如,阿伯克龙比和惠誉赚取高额利润通过出售used-looking服装被认为是时髦和青少年所要
网络安全外文翻译文献
网络安全外文翻译文献 (文档含英文原文和中文翻译) 翻译： 计算机网络安全与防范 1.1引言 计算机技术的飞速发展提供了一定的技术保障，这意味着计算机应用已经渗透到社会的各个领域。在同一时间，巨大的进步和网络技术的普及，社会带来了巨大的经济利润。然而，在破坏和攻击计算机信息系统的方法已经改变了很多的网络环境下，网络安全问题逐渐成为计算机安全的主流。
1.2网络安全 1.2.1计算机网络安全的概念和特点 计算机网络的安全性被认为是一个综合性的课题，由不同的人，包括计算机科学、网络技术、通讯技术、信息安全技术、应用数学、信息理论组成。作为一个系统性的概念，网络的安全性由物理安全、软件安全、信息安全和流通安全组成。从本质上讲，网络安全是指互联网信息安全。一般来说，安全性、集成性、可用性、可控性是关系到网络信息的相关理论和技术，属于计算机网络安全的研究领域。相反，狭隘“网络信息安全”是指网络安全，这是指保护信息秘密和集成，使用窃听、伪装、欺骗和篡夺系统的安全性漏洞等手段，避免非法活动的相关信息的安全性。总之，我们可以保护用户利益和验证用户的隐私。 计算机网络安全有保密性、完整性、真实性、可靠性、可用性、非抵赖性和可控性的特点。 隐私是指网络信息不会被泄露给非授权用户、实体或程序，但是授权的用户除外，例如，电子邮件仅仅是由收件人打开，其他任何人都不允许私自这样做。隐私通过网络信息传输时，需要得到安全保证。积极的解决方案可能会加密管理信息。虽然可以拦截，但它只是没有任何重要意义的乱码。 完整性是指网络信息可以保持不被修改、破坏，并在存储和传输过程中丢失。诚信保证网络的真实性，这意味着如果信息是由第三方或未经授权的人检查，内容仍然是真实的和没有被改变的。因此保持完整性是信息安全的基本要求。 可靠性信息的真实性主要是确认信息所有者和发件人的身份。 可靠性表明该系统能够在规定的时间和条件下完成相关的功能。这是所有的网络信息系统的建立和运作的基本目标。 可用性表明网络信息可被授权实体访问，并根据自己的需求使用。 不可抵赖性要求所有参加者不能否认或推翻成品的操作和在信息传输过程中的承诺。
建筑-外文翻译
外文文献： Risk Analysis of the International Construction Project By: Paul Stanford Kupakuwana Cost Engineering Vol. 51/No. 9 September 2009 ABSTRACT This analysis used a case study methodology to analyse the issues surrounding the partial collapse of the roof of a building housing the headquarters of the Standards Association of Zimbabwe (SAZ). In particular, it examined the prior roles played by the team of construction professionals. The analysis revealed that the SAZ’s traditional construction project was generally characterized by high risk. There was a clear indication of the failure of a contractor and architects in preventing and/or mitigating potential construction problems as alleged by the plaintiff. It was reasonable to conclude that between them the defects should have been detected earlier and rectified in good time before the partial roof failure. It appeared justified for the plaintiff to have brought a negligence claim against both the contractor and the architects. The risk analysis facilitated, through its multi-dimensional approach to a critical examination of a construction problem, the identification of an effective risk management strategy for future construction projects. It further served to emphasize the point that clients are becoming more demanding, more discerning, and less willing to accept risk without recompense. Clients do not want surprise, and are more likely to engage in litigation when things go wrong. KEY WORDS:Arbitration, claims, construction, contracts, litigation, project and risk The structural design of the reinforced concrete elements was done by consulting engineers Knight Piesold (KP). Quantity surveying services were provided by Hawkins, Leshnick & Bath (HLB). The contract was awarded to Central African Building Corporation (CABCO) who was also responsible for the provision of a specialist roof structure using patented “gang nail” roof
外文翻译中文版(完整版)
毕业论文外文文献翻译 毕业设计（论文）题目关于企业内部环境绩效审计的研究翻译题目最高审计机关的环境审计活动 学院会计学院 专业会计学 姓名张军芳 班级09020615 学号09027927 指导教师何瑞雄
最高审计机关的环境审计活动 1最高审计机关越来越多的活跃在环境审计领域。特别是1993-1996年期间，工作组已检测到环境审计活动坚定的数量增长。首先，越来越多的最高审计机关已经活跃在这个领域。其次是积极的最高审计机关，甚至变得更加活跃：他们分配较大部分的审计资源给这类工作，同时出版更多环保审计报告。表1显示了平均数字。然而，这里是机构间差异较大。例如，环境报告的数量变化，每个审计机关从1到36份报告不等。 1996-1999年期间，结果是不那么容易诠释。第一，活跃在环境审计领域的最高审计机关数量并没有太大变化。“活性基团”的组成没有保持相同的：一些最高审计机关进入，而其他最高审计机关离开了团队。环境审计花费的时间量略有增加。二，但是，审计报告数量略有下降，1996年和1999年之间。这些数字可能反映了从量到质的转变。这个信号解释了在过去三年从规律性审计到绩效审计的转变（1994-1996年，20％的规律性审计和44％绩效审计;1997-1999：16％规律性审计和绩效审计54％）。在一般情况下，绩效审计需要更多的资源。我们必须认识到审计的范围可能急剧变化。在将来，再将来开发一些其他方式去测算人们工作量而不是计算通过花费的时间和发表的报告会是很有趣的。 在2000年，有62个响应了最高审计机关并向工作组提供了更详细的关于他们自1997年以来公布的工作信息。在1997-1999年，这62个最高审计机关公布的560个环境审计报告。当然，这些报告反映了一个庞大的身躯，可用于其他机构的经验。环境审计报告的参考书目可在网站上的最高审计机关国际组织的工作组看到。这里这个信息是用来给最高审计机关的审计工作的内容更多一些洞察。 自1997年以来，少数环境审计是规律性审计（560篇报告中有87篇，占16％）。大多数审计绩效审计（560篇报告中有304篇，占54％），或组合的规律性和绩效审计（560篇报告中有169篇，占30％）。如前文所述，绩效审计是一个广泛的概念。在实践中，绩效审计往往集中于环保计划的实施（560篇报告中有264篇，占47％），符合国家环保法律，法规的，由政府部门，部委和/或其他机构的任务给访问（560篇报告中有212篇，占38％）。此外，审计经常被列入政府的环境管理系统（560篇报告中有156篇，占28％）。下面的元素得到了关注审计报告：影响或影响现有的国家环境计划非环保项目对环境的影响;环境政策;由政府遵守国际义务和承诺的10％至20％。许多绩效审计包括以上提到的要素之一。 1本文译自：S. Van Leeuwen.(2004).’’Developments in Environmental Auditing by Supreme Audit Institutions’’ Environmental Management Vol. 33, No. 2, pp. 163–1721
毕业设计外文翻译
毕业设计（论文） 外文翻译 题目西安市水源工程中的 水电站设计 专业水利水电工程 班级 学生 指导教师 2016年
研究钢弧形闸门的动态稳定性 牛志国 河海大学水利水电工程学院，中国南京，邮编210098 nzg_197901@https://www.wendangku.net/doc/da8277088.html,，niuzhiguo@https://www.wendangku.net/doc/da8277088.html, 李同春 河海大学水利水电工程学院，中国南京，邮编210098 ltchhu@https://www.wendangku.net/doc/da8277088.html, 摘要 由于钢弧形闸门的结构特征和弹力，调查对参数共振的弧形闸门的臂一直是研究领域的热点话题弧形弧形闸门的动力稳定性。在这个论文中，简化空间框架作为分析模型，根据弹性体薄壁结构的扰动方程和梁单元模型和薄壁结构的梁单元模型，动态不稳定区域的弧形闸门可以通过有限元的方法，应用有限元的方法计算动态不稳定性的主要区域的弧形弧形闸门工作。此外，结合物理和数值模型，对识别新方法的参数共振钢弧形闸门提出了调查，本文不仅是重要的改进弧形闸门的参数振动的计算方法，但也为进一步研究弧形弧形闸门结构的动态稳定性打下了坚实的基础。 简介 低举升力，没有门槽，好流型，和操作方便等优点，使钢弧形闸门已经广泛应用于水工建筑物。弧形闸门的结构特点是液压完全作用于弧形闸门，通过门叶和主大梁，所以弧形闸门臂是主要的组件确保弧形闸门安全操作。如果周期性轴向载荷作用于手臂，手臂的不稳定是在一定条件下可能发生。调查指出:在弧形闸门的20次事故中，除了极特殊的破坏情况下，弧形闸门的破坏的原因是弧形闸门臂的不稳定;此外，明显的动态作用下发生破坏。例如:张山闸，位于中国的江苏省，包括36个弧形闸门。当一个弧形闸门打开放水时，门被破坏了，而其他弧形闸门则关闭，受到静态静水压力仍然是一样的，很明显，一个动态的加载是造成的弧形闸门破坏一个主要因素。因此弧形闸门臂的动态不稳定是造成弧形闸门(特别是低水头的弧形闸门)破坏的主要原是毫无疑问。
5外文翻译原文1
A Case Study of Pattern-based Software Framework to Improve the Quality of Software Development Chih-Hung Chang, Chih-Wei Lu Dept. of Information Management, Hsiuping Institute of Technology No.11, Gongye Rd., Dali City, Taichung County, Taiwan(R.O.C.) 886-4-24961123 ext 3112 {chchang,cwlu}@ https://www.wendangku.net/doc/da8277088.html,.tw William C. Chu Dept. of Computer Science and Information Engineering, Tunghai University No.181, Sec. 3, Taichung Port Rd.,Taichung City, Taiwan (R.O.C.) 886-4-23508983 cchu@https://www.wendangku.net/doc/da8277088.html,.tw Nien-Lin Hsueh Dept. of Information Engineering and Computer Science, Feng Chia University No. 100 Wenhwa Rd., Taichung, Taiwan (R.O.C.) 886-4- 24517250 ext 3773 nlhsueh@https://www.wendangku.net/doc/da8277088.html,.tw Chorng-Shiuh Koong Dept. of Computer and Information Science, Taichung University No.140, Ming-Sheng Rd., Taichung City, Taiwan (R.O.C.) 886-4-22183804 csko@https://www.wendangku.net/doc/da8277088.html,.tw ABSTRACT In recent years, development of the software industry and demand for software systems have increased rapidly, but developers often does not know whose suggestion to follow regarding methodologies of software engineering. One reason for that is the difficulty in applying new software engineering technologies. Developers take a long time to train. Another reason is the difficulty in integrating CASE toolsets. So many indeterminate factors make the development process more and more complex. On the other hand, software development is too customized, and software reuse is difficult. T he reasons above are the cause for software development and maintenance to become more complex and difficult to control. In this paper we explore the importation of a software pattern-based framework, and the development of an ERP/support chain system. Based on software patterns, developers can separate development and business so as to reduce problems caused by the developer’s lack of business experience. T he quality of the product can thus be enhanced, software development costs be reduced, and software maintenance be improved. Keywords Design Pattern, Framework, Software Development Process, XML 1.INTRODUCTION In Object-Oriented T echnology, the property of inheritance allows software components to be reused, which can obviously reduce the cost of software development. For this reason, to produce a highly reusable software component is an important goal of software engineering. However, programmers are usually focused on code reuse while ignoring design reuse. Design patterns provide a clear concept of design structure by describing the relationships of inheritance and reference between components of the system. Design patterns are a series of familiar usages and constructions utilized throughout system design. Design patterns allow rapid coding of certain components by following certain patterns of steps. T his can improve the documentation and maintenance of existing systems by providing an explicit specification of class, object interactions and their underlying intents. One of the main purposes of design patterns is to help software engineers to understand the common characteristics of software objects/components in specialized domain. In recent years, due to the development and maturation of WWW and Java [14] technologies, many applications are now web applications or leaning in that direction. Many software concepts are utilized for the web as well, such as Design Patterns and Frameworks. The Apache Struts [12] and Spring Framework [13] are both open source frameworks used to address and reduce the complexity of developing an enterprise application. T he advantage of using a framework is the layered architecture it provides. Layered architecture allowed users to choose the component desired, while also providing the integration framework when developing application using J2EE. T hese developing web concepts can facilitate the development of web applications. However, these very useful tools and concepts lack a systematic organization. We hope to use these open source software technologies to develop a software framework which can be applied to web application. T his should solve the problem of web applications lacking a good structure, while through applying these open source software technologies, software development costs will be reduced. Furthermore, a guideline for programmers who wants to use these open source technologies will be provided. This paper is organized as follows: In the next section, we discuss works related to our project; in section 3, the open source technologies used in the paper and the system implementation will be described; Section 4 is a sample experiment. T he conclusion is given in section 5.