12 24小时数字时钟VHDL设计

报时电路
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;

entity ly4948_baoshi is
port(clk_2KHz,clk_1KHz,clk1Hz:in std_logic;
bcd10S,bcd1S,bcd10M,bcd1M:in std_logic_vector(3 downto 0);
clkout:out std_logic);
end ly4948_baoshi;

architecture bav of ly4948_baoshi is
signal clkout_1:std_logic;
begin
process(bcd10S,bcd1S,bcd10M,bcd1M,clk_2KHz,clk_1KHz,clk1Hz)
begin
if (bcd10M="0101" and bcd1M="1001") and (bcd10S="0101") and (bcd1S>4) and (bcd1S<=9) then

if clk1Hz='1' then
clkout_1<=clk_1KHz;
else
clkout_1<='Z';
end if;
elsif (bcd10M="0000" and bcd1M="0000") and (bcd10S="0000") and (bcd1S="0000") then
if clk1Hz='1' then
clkout_1<=clk_2KHz;
else
clkout_1<='Z';
end if;
else
clkout_1<='Z';
end if;
clkout<=clkout_1;
end process;
end bav;


12 24小时转换电路

library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;

entity ly4948_cnt12_24 is
port(clk,contr12_24:in std_logic;
bcd10,bcd1:out std_logic_vector(3 downto 0));
end ly4948_cnt12_24;

architecture behav of ly4948_cnt12_24 is
type ly is(s0,s1,s2,s3,s4,s5,s6,s7,s8,s9,s10,s11,s12,s13,s14,s15,s16,s17,s18,s19,s20,s21,s22,s23);
signal p,n:ly;
signal b10,b1:std_logic_vector(3 downto 0);
begin
process(clk)
begin
if clk'event and clk='1' then
p<=n;
end if;
end process;
process(p,contr12_24)
begin
case p is
when s0=> if contr12_24='0' then
b10<="0000";
b1<="0000";
else
b10<="0001";
b1<="0010";
end if;
n<=s1;
when s1=> b10<="0000";
b1<="0001";
n<=s2;
when s2=> b10<="0000";
b1<="0010";
n<=s3;
when s3=> b10<="0000";
b1<="0011";
n<=s4;
when s4 =>b10<="0000";
b1<="0100";
n<=s5;
when s5 =>b10<="0000";
b1<="0101";
n<=s6;
when s6 =>b10<="0000";
b1<="0110";
n<=s7;
when s7 =>b10<="0000";
b1<="0111";
n<=s8;
when s8 =>b10<="0000";
b1<="1000";
n<=s9;
when s9 =>b10<="0000";
b1<="0101";
n<=s10;
when s10 =>b10<="0001";
b1<="0000";
n<=s11;
when s11 =>b10<="0001";
b1<="0001";
n<=s12;
when s12 =>b10<="0001";
b1<="0010";
n<=s13;
when s13 =>if contr12_24='0' then

b10<="0001";
b1<="0011";
else
b10<="0000";
b1<="0001";
end if;
n<=s14;
when s14 =>if contr12_24='0' then
b10<="0001";
b1<="0100";
else
b10<="0000";
b1<="0010";
end if;
n<=s15;
when s15 =>if contr12_24='0' then
b10<="0001";
b1<="0101";
else
b10<="0000";
b1<="0011";
end if;
n<=s16;
when s16 =>if contr12_24='0' then
b10<="0001";
b1<="0110";
else
b10<="0000";
b1<="0100";
end if;
n<=s17;
when s17 =>if contr12_24='0' then
b10<="0001";
b1<="0111";
else
b10<="0000";
b1<="0101";
end if;
n<=s18;
when s18 =>if contr12_24='0' then
b10<="0001";
b1<="1000";
else
b10<="0000";
b1<="0110";
end if;
n<=s19;
when s19 =>if contr12_24='0' then
b10<="0001";
b1<="1001";
else
b10<="0000";
b1<="0111";
end if;
n<=s20;
when s20 =>if contr12_24='0' then
b10<="0010";
b1<="0000";
else
b10<="0000";
b1<="1000";
end if;
n<=s21;
when s21 =>if contr12_24='0' then
b10<="0010";
b1<="0001";
else
b10<="0000";
b1<="1001";
end if;
n<=s22;
when s22 =>if contr12_24='0' then
b10<="0010";
b1<="0010";
else
b10<="0001";
b1<="0000";
end if;
n<=s23;
when s23 =>if contr12_24='0' then
b10<="0010";
b1<="0011";
else
b10<="0001";
b1<="0001";
end if;
n<=s0;
when others=>null;
end case;
end process;
bcd10<=b10;
bcd1<=b1;
end behav;

动态译码

器display

library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;

entity ly4948_disp is
port(din0,din1,din2,din3,din4,din5:in std_logic_vector(3 downto 0);
clk:in std_logic;
led_sa,led_sb,led_sc:out std_logic;
led_a,led_b,led_c,led_d,led_e:out std_logic;
led_f,led_g,led_dp:out std_logic);
end ly4948_disp;

architecture bav of ly4948_disp is
signal seg:std_logic_vector(6 downto 0);
signal sel:std_logic_vector(2 downto 0);
signal num:std_logic_vector(3 downto 0);
signal s:std_logic_vector(2 downto 0);
begin
led_sa<=sel(0);
led_sb<=sel(1);
led_sc<=sel(2);
led_a<=seg(0);
led_b<=seg(1);
led_c<=seg(2);
led_d<=seg(3);
led_e<=seg(4);
led_f<=seg(5);
led_g<=seg(6);
process(clk)
begin
if clk'event and clk='1' then
if s="101" then
s<="000";
else
s<=s+'1';
end if;
end if;
end process;

process(s,din0,din1,din2,din3,din4,din5)
begin
if s="000" then
sel<="000";
num<=din0;
led_dp<='0';
elsif s="001" then
sel<="001";
num<=din1;
led_dp<='0';
elsif s="010" then
sel<="010";
num<=din2;
led_dp<='0';
elsif s="011" then
sel<="011";
num<=din3;
led_dp<='0';
elsif s="100" then
sel<="100";
num<=din4;
led_dp<='0';
elsif s="101" then
sel<="101";
num<=din5;
led_dp<='0';
else
sel<="XXX";
num<="XXXX";
led_dp<='0';
end if;
end process;
seg<="0111111" when num=0 else
"0000110" when num=1 else
"1011011" when num=2 else
"1001111" when num=3 else
"1100110" when num=4 else
"1101101" when num=5 else
"1111101" when num=6 else
"0000111" when num=7 else
"1111111" when num=8 else
"1101111" when num=9 else
"1110111" when num=10 else
"1111100" when num=11 else
"0111001" when num=12 else
"1011110" when num=13 else
"1111001" when num=14 else
"1110001" when num=15 else
"0000000";
end bav;

2选1选择器

library ieee;
use ieee.std_logic_1164.all;

entity ly4948_mux2 is
port(sel,a,b:in std_logic;
q:out std_logic);
end ly4948_mux2;

architecture bav of ly4948_mux2 is
begin
process(sel,a,b)
begin
if sel='1' then
q<=a;
else
q<=b;
end if;
end process;
end bav;